linux-kernel - Re: [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead, c900-plic request_threaded

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Mon, 1 Nov 2021 10:00:32 +0800
From:   Guo Ren <guoren@...nel.org>
To:     Nikita Shubin <nikita.shubin@...uefel.me>
Cc:     Marc Zyngier <maz@...nel.org>, Anup Patel <anup@...infault.org>,
        Atish Patra <atish.patra@....com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Palmer Dabbelt <palmer@...belt.com>,
        Heiko Stübner <heiko@...ech.de>,
        Rob Herring <robh@...nel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        linux-riscv <linux-riscv@...ts.infradead.org>,
        Guo Ren <guoren@...ux.alibaba.com>
Subject: Re: [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead, c900-plic
 request_threaded_irq with ONESHOT

Thx Nikita,

I would fixup that globally in the plic in next version of patch.

On Thu, Oct 28, 2021 at 7:01 PM Nikita Shubin <nikita.shubin@...uefel.me> wrote:
>
> Hello Marc and Guo Ren!
>
> On Mon, 25 Oct 2021 11:48:33 +0100
> Marc Zyngier <maz@...nel.org> wrote:
>
> > On Sun, 24 Oct 2021 02:33:03 +0100,
> > guoren@...nel.org wrote:
> > >
> > > From: Guo Ren <guoren@...ux.alibaba.com>
> > >
> > > When using "devm_request_threaded_irq(,,,,IRQF_ONESHOT,,)" in the
> > > driver, only the first interrupt could be handled, and continue irq
> > > is blocked by hw. Because the thead,c900-plic couldn't complete
> > > masked irq source which has been disabled in enable register. Add
> > > thead_plic_chip which fix up c906-plic irq source completion
> > > problem by unmask/mask wrapper.
> > >
> > > Here is the description of Interrupt Completion in PLIC spec [1]:
> > >
> > > The PLIC signals it has completed executing an interrupt handler by
> > > writing the interrupt ID it received from the claim to the
> > > claim/complete register. The PLIC does not check whether the
> > > completion ID is the same as the last claim ID for that target. If
> > > the completion ID does not match an interrupt source that is
> > > currently enabled for the target, the ^^ ^^^^^^^^^ ^^^^^^^
> > > completion is silently ignored.
> >
> > Given this bit of the spec...
> >
> > > +static void plic_thead_irq_eoi(struct irq_data *d)
> > > +{
> > > +   struct plic_handler *handler =
> > > this_cpu_ptr(&plic_handlers); +
> > > +   if (irqd_irq_masked(d)) {
> > > +           plic_irq_unmask(d);
> > > +           writel(d->hwirq, handler->hart_base +
> > > CONTEXT_CLAIM);
> > > +           plic_irq_mask(d);
> > > +   } else {
> > > +           writel(d->hwirq, handler->hart_base +
> > > CONTEXT_CLAIM);
> > > +   }
> > > +}
> > > +
> >
> > ... it isn't obvious to me why this cannot happen on an SiFive PLIC.
>
> This indeed happens with SiFive PLIC. I am currently tinkering with
> da9063 RTC on SiFive Unmatched, and ALARM irq fires only once. However
> with changes proposed by Guo Ren in plic_thead_irq_eoi, everything
> begins to work fine.
>
> May be these change should be propagated to plic_irq_eoi instead of
> making a new function ?
>
> >
> > And it isn't only for threaded interrupts in oneshot mode. Any driver
> > can mask an interrupt from its handler after having set the
> > IRQ_DISABLE_UNLAZY flag, and the interrupt would need the exact same
> > treatment.
> >
> >       M.
> >
>
> ---
> diff --git a/drivers/irqchip/irq-sifive-plic.c
> b/drivers/irqchip/irq-sifive-plic.c index cf74cfa82045..259065d271ef
> 100644 --- a/drivers/irqchip/irq-sifive-plic.c
> +++ b/drivers/irqchip/irq-sifive-plic.c
> @@ -163,7 +163,13 @@ static void plic_irq_eoi(struct irq_data *d)
>  {
>         struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
>
> -       writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM);
> +       if (irqd_irq_masked(d)) {
> +               plic_irq_unmask(d);
> +               writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM);
> +               plic_irq_mask(d);
> +       } else {
> +               writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM);
> +       }
>  }
>
>  static struct irq_chip plic_chip = {



-- 
Best Regards
 Guo Ren

ML: https://lore.kernel.org/linux-csky/