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Message-ID: <87ee809qes.wl-maz@kernel.org>
Date: Mon, 01 Nov 2021 09:27:39 +0000
From: Marc Zyngier <maz@...nel.org>
To: Anup Patel <anup@...infault.org>
Cc: Guo Ren <guoren@...nel.org>,
Nikita Shubin <nikita.shubin@...uefel.me>,
Atish Patra <atish.patra@....com>,
Thomas Gleixner <tglx@...utronix.de>,
Palmer Dabbelt <palmer@...belt.com>,
Heiko Stübner <heiko@...ech.de>,
Rob Herring <robh@...nel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
linux-riscv <linux-riscv@...ts.infradead.org>,
Guo Ren <guoren@...ux.alibaba.com>
Subject: Re: [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead, c900-plic request_threaded_irq with ONESHOT
On Mon, 01 Nov 2021 04:27:50 +0000,
Anup Patel <anup@...infault.org> wrote:
> The RISC-V AIA will totally replace RISC-V PLIC going forward. In fact,
> RISC-V AIA APLIC addresses all limitations of RISC-V PLIC along with
> new features additions.
Instead of arguing about yet another piece of RISC-V vapourware, how
about you guys propose a patch that would actually make the *current*
HW work to some extent?
M.
--
Without deviation from the norm, progress is not possible.
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