Message-ID: <CAJF2gTRwi+yH-hQ0SHKDOuUf=OOMfJxQb6Q5m6xRCPjvbYjqaQ@mail.gmail.com>
Date:   Mon, 1 Nov 2021 11:57:04 +0800
From:   Guo Ren <guoren@...nel.org>
To:     Anup Patel <anup@...infault.org>
Cc:     Marc Zyngier <maz@...nel.org>,
        Nikita Shubin <nikita.shubin@...uefel.me>,
        Atish Patra <atish.patra@....com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Palmer Dabbelt <palmer@...belt.com>,
        Heiko Stübner <heiko@...ech.de>,
        Rob Herring <robh@...nel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        linux-riscv <linux-riscv@...ts.infradead.org>,
        Guo Ren <guoren@...ux.alibaba.com>
Subject: Re: [PATCH V5 3/3] irqchip/sifive-plic: Fixup thead, c900-plic
 request_threaded_irq with ONESHOT

On Mon, Nov 1, 2021 at 10:53 AM Anup Patel <anup@...infault.org> wrote:
>
> On Mon, Nov 1, 2021 at 7:50 AM Guo Ren <guoren@...nel.org> wrote:
> >
> > On Thu, Oct 28, 2021 at 10:58 PM Marc Zyngier <maz@...nel.org> wrote:
> > >
> > > On Thu, 28 Oct 2021 11:55:23 +0100,
> > > Nikita Shubin <nikita.shubin@...uefel.me> wrote:
> > > >
> > > > Hello Marc and Guo Ren!
> > > >
> > > > On Mon, 25 Oct 2021 11:48:33 +0100
> > > > Marc Zyngier <maz@...nel.org> wrote:
> > > >
> > > > > On Sun, 24 Oct 2021 02:33:03 +0100,
> > > > > guoren@...nel.org wrote:
> > > > > >
> > > > > > From: Guo Ren <guoren@...ux.alibaba.com>
> > > > > >
> > > > > > When using "devm_request_threaded_irq(,,,,IRQF_ONESHOT,,)" in the
> > > > > > driver, only the first interrupt could be handled, and continue irq
> > > > > > is blocked by hw. Because the thead,c900-plic couldn't complete
> > > > > > masked irq source which has been disabled in enable register. Add
> > > > > > thead_plic_chip which fix up c906-plic irq source completion
> > > > > > problem by unmask/mask wrapper.
> > > > > >
> > > > > > Here is the description of Interrupt Completion in PLIC spec [1]:
> > > > > >
> > > > > > The PLIC signals it has completed executing an interrupt handler by
> > > > > > writing the interrupt ID it received from the claim to the
> > > > > > claim/complete register. The PLIC does not check whether the
> > > > > > completion ID is the same as the last claim ID for that target. If
> > > > > > the completion ID does not match an interrupt source that is
> > > > > > currently enabled for the target, the ^^ ^^^^^^^^^ ^^^^^^^
> > > > > > completion is silently ignored.
> > > > >
> > > > > Given this bit of the spec...
> > > > >
> > > > > > +static void plic_thead_irq_eoi(struct irq_data *d)
> > > > > > +{
> > > > > > + struct plic_handler *handler =
> > > > > > this_cpu_ptr(&plic_handlers); +
> > > > > > + if (irqd_irq_masked(d)) {
> > > > > > +         plic_irq_unmask(d);
> > > > > > +         writel(d->hwirq, handler->hart_base +
> > > > > > CONTEXT_CLAIM);
> > > > > > +         plic_irq_mask(d);
> > > > > > + } else {
> > > > > > +         writel(d->hwirq, handler->hart_base +
> > > > > > CONTEXT_CLAIM);
> > > > > > + }
> > > > > > +}
> > > > > > +
> > > > >
> > > > > ... it isn't obvious to me why this cannot happen on an SiFive PLIC.
> > > >
> > > > This indeed happens with SiFive PLIC. I am currently tinkering with
> > > > da9063 RTC on SiFive Unmatched, and ALARM irq fires only once. However
> > > > with changes proposed by Guo Ren in plic_thead_irq_eoi, everything
> > > > begins to work fine.
> > > >
> > > > May be these change should be propagated to plic_irq_eoi instead of
> > > > making a new function ?
> > >
> > > That's my impression too. I think the T-Head defect is pretty much
> > > immaterial when you consider how 'interesting' the PLIC architecture
> > > is.
> > Which is the "T-Head defect" you mentioned here?
> >  1. Auto masking with claim + complete (I don't think it's a defect,
> > right? May I add a new patch to utilize the feature to decrease a
> > little duplicate mask/unmask operations in the future?)
>
> This is definitely a defect and non-compliance for T-HEAD because
I just agree with non-compliance, but what's the defect of
auto-masking? If somebody could explain, I'm very grateful.

> no sane interrupt controller would mask interrupt upon claim and this
> is not what RISC-V PLIC defines.
>
> >  2. EOI failed when masked
>
> This defect exists for both RISC-V PLIC and T-HEAD PLIC
> because of the way interrupt completion is defined.
>
> >
> > > Conflating EOI and masking really is a misfeature...
> > I think the problem is riscv PLIC reuse enable bit as mask bit. I
> > recommend separating them. That means:
>
> There are no per-interrupt mask bits. We only have per-context
> and per-interrupt enable bits which is used to provide mask/unmask
> functionality expected by the irqchip framework.
>
> I don't see how this is a problem for RISC-V PLIC. The only real
> issue with RISC-V PLIC is the fact the interrupt completion will be
> ignored for a masked interrupt which is what Marc is pointing at.
So you are not considering add per-interrupt mask bits to solve the
above problem, right?

I don't think you would keep below codes in AIA eoi.
 +             plic_irq_unmask(d);
 +             writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM);
 +             plic_irq_mask(d);

>
> Regards,
> Anup
>
> >  - EOI still depends on enable bit.
> >  - Add mask/unmask bit regs to do the right thing.
>
>
>
> >
> > >
> > >         M.
> > >
> > > --
> > > Without deviation from the norm, progress is not possible.
> >
> >
> >
> > --
> > Best Regards
> >  Guo Ren
> >
> > ML: https://lore.kernel.org/linux-csky/



-- 
Best Regards
 Guo Ren

ML: https://lore.kernel.org/linux-csky/

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