linux-kernel - Re: [PATCH v2 07/13] clk: imx: Add initial support for i.MXRT clock driver

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Message-ID: <CAOMZO5C9wY-BRbF-3D+mvaK3DaYi1kURt5QX-r3=umqpsT+hhw@mail.gmail.com>
Date:   Tue, 2 Nov 2021 20:34:26 -0300
From:   Fabio Estevam <festevam@...il.com>
To:     Jesse Taube <mr.bossman075@...il.com>
Cc:     NXP Linux Team <linux-imx@....com>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Shawn Guo <shawnguo@...nel.org>,
        Sascha Hauer <s.hauer@...gutronix.de>,
        Sascha Hauer <kernel@...gutronix.de>,
        Ulf Hansson <ulf.hansson@...aro.org>,
        Dong Aisheng <aisheng.dong@....com>,
        Stefan Agner <stefan@...er.ch>,
        Linus Walleij <linus.walleij@...aro.org>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Arnd Bergmann <arnd@...db.de>, Olof Johansson <olof@...om.net>,
        soc@...nel.org, Russell King - ARM Linux <linux@...linux.org.uk>,
        Abel Vesa <abel.vesa@....com>,
        Adrian Hunter <adrian.hunter@...el.com>,
        Jiri Slaby <jirislaby@...nel.org>,
        Giulio Benetti <giulio.benetti@...ettiengineering.com>,
        Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@...hiba.co.jp>,
        linux-clk <linux-clk@...r.kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>,
        "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" 
        <linux-arm-kernel@...ts.infradead.org>,
        linux-kernel <linux-kernel@...r.kernel.org>,
        linux-mmc <linux-mmc@...r.kernel.org>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
        linux-serial@...r.kernel.org
Subject: Re: [PATCH v2 07/13] clk: imx: Add initial support for i.MXRT clock driver

On Tue, Nov 2, 2021 at 7:57 PM Jesse Taube <mr.bossman075@...il.com> wrote:

> +#include "clk.h"
> +#define ANATOP_BASE_ADDR       0x400d8000

This is now unused. Please remove it.

> +       clk[IMXRT1050_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", ccm_base + 0x80, 2);
> +       clk[IMXRT1050_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", ccm_base + 0x80, 4);
> +       clk[IMXRT1050_CLK_LPUART1] = imx_clk_gate2("lpuart1", "lpuart_podf", ccm_base + 0x7c, 24);
> +       clk[IMXRT1050_CLK_LCDIF_APB] = imx_clk_gate2("lcdif", "lcdif_podf", ccm_base + 0x74, 10);
> +       clk[IMXRT1050_CLK_DMA] = imx_clk_gate("dma", "ipg", ccm_base + 0x7C, 6);
> +       clk[IMXRT1050_CLK_DMA_MUX] = imx_clk_gate("dmamux0", "ipg", ccm_base + 0x7C, 7);

The imx clock drivers have been converted to the clk_hw API.

For a reference, please check:
f1541e15e38e ("clk: imx6sx: Switch to clk_hw based API")

The same conversion could be done here.

> +       imx_check_clocks(clk, ARRAY_SIZE(clk));
> +       clk_data.clks = clk;
> +       clk_data.clk_num = ARRAY_SIZE(clk);
> +       of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
> +       clk_prepare_enable(clk[IMXRT1050_CLK_PLL1_ARM]);
> +       clk_prepare_enable(clk[IMXRT1050_CLK_PLL2_SYS]);
> +       clk_prepare_enable(clk[IMXRT1050_CLK_PLL3_USB_OTG]);
> +       clk_prepare_enable(clk[IMXRT1050_CLK_PLL3_PFD1_664_62M]);
> +       clk_prepare_enable(clk[IMXRT1050_CLK_PLL2_PFD2_396M]);

If these clocks are essential for the SoC to work, then you could pass
the CLK_IS_CRITICAL flag instead of calling clk_prepare_enable()