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Message-ID: <1635836275-8873-1-git-send-email-quic_fenglinw@quicinc.com>
Date: Tue, 2 Nov 2021 14:57:35 +0800
From: Fenglin Wu <quic_fenglinw@...cinc.com>
To: <linux-arm-msm@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<sboyd@...nel.org>, Andy Gross <agross@...nel.org>,
Bjorn Andersson <bjorn.andersson@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Fenglin Wu <quic_fenglinw@...cinc.com>,
<devicetree@...r.kernel.org>
CC: <collinsd@...eaurora.org>, <subbaram@...eaurora.org>
Subject: [PATCH v1] dt-bindings: convert qcom,spmi-pmic-arb binding to YAML format
Convert the SPMI PMIC arbiter documentation to JSON/yaml.
Signed-off-by: Fenglin Wu <quic_fenglinw@...cinc.com>
---
.../bindings/spmi/qcom,spmi-pmic-arb.txt | 67 -----------
.../bindings/spmi/qcom,spmi-pmic-arb.yaml | 122 +++++++++++++++++++++
2 files changed, 122 insertions(+), 67 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt
create mode 100644 Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml
diff --git a/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt
deleted file mode 100644
index 6332507..0000000
--- a/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.txt
+++ /dev/null
@@ -1,67 +0,0 @@
-Qualcomm SPMI Controller (PMIC Arbiter)
-
-The SPMI PMIC Arbiter is found on Snapdragon chipsets. It is an SPMI
-controller with wrapping arbitration logic to allow for multiple on-chip
-devices to control a single SPMI master.
-
-The PMIC Arbiter can also act as an interrupt controller, providing interrupts
-to slave devices.
-
-See Documentation/devicetree/bindings/spmi/spmi.yaml for the generic SPMI
-controller binding requirements for child nodes.
-
-See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt for
-generic interrupt controller binding documentation.
-
-Required properties:
-- compatible : should be "qcom,spmi-pmic-arb".
-- reg-names : must contain:
- "core" - core registers
- "intr" - interrupt controller registers
- "cnfg" - configuration registers
- Registers used only for V2 PMIC Arbiter:
- "chnls" - tx-channel per virtual slave registers.
- "obsrvr" - rx-channel (called observer) per virtual slave registers.
-
-- reg : address + size pairs describing the PMIC arb register sets; order must
- correspond with the order of entries in reg-names
-- #address-cells : must be set to 2
-- #size-cells : must be set to 0
-- qcom,ee : indicates the active Execution Environment identifier (0-5)
-- qcom,channel : which of the PMIC Arb provided channels to use for accesses (0-5)
-
-Optional properties:
-- interrupts : interrupt list for the PMIC Arb controller, must contain a
- single interrupt entry for the peripheral interrupt
-- interrupt-names : corresponding interrupt names for the interrupts
- listed in the 'interrupts' property, must contain:
- "periph_irq" - summary interrupt for PMIC peripherals
-- interrupt-controller : boolean indicator that the PMIC arbiter is an interrupt controller
-- #interrupt-cells : must be set to 4. Interrupts are specified as a 4-tuple:
- cell 1: slave ID for the requested interrupt (0-15)
- cell 2: peripheral ID for requested interrupt (0-255)
- cell 3: the requested peripheral interrupt (0-7)
- cell 4: interrupt flags indicating level-sense information, as defined in
- dt-bindings/interrupt-controller/irq.h
-
-Example:
-
- spmi {
- compatible = "qcom,spmi-pmic-arb";
- reg-names = "core", "intr", "cnfg";
- reg = <0xfc4cf000 0x1000>,
- <0xfc4cb000 0x1000>,
- <0xfc4ca000 0x1000>;
-
- interrupt-names = "periph_irq";
- interrupts = <0 190 0>;
-
- qcom,ee = <0>;
- qcom,channel = <0>;
-
- #address-cells = <2>;
- #size-cells = <0>;
-
- interrupt-controller;
- #interrupt-cells = <4>;
- };
diff --git a/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml
new file mode 100644
index 0000000..05bb114
--- /dev/null
+++ b/Documentation/devicetree/bindings/spmi/qcom,spmi-pmic-arb.yaml
@@ -0,0 +1,122 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spmi/qcom,spmi-pmic-arb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SPMI PMIC Arbiter
+
+maintainers:
+ - Fenglin Wu <quic_fenglinw@...cinc.com>
+
+description: |
+ The SPMI PMIC Arbiter is found on Snapdragon chipsets. It is an SPMI
+ controller with wrapping arbitration logic to allow for multiple
+ on-chip devices to control a single SPMI master.
+
+ The PMIC Arbiter can also act as an interrupt controller, providing
+ interrupts to slave devices.
+
+ See Documentation/devicetree/bindings/spmi/spmi.yaml for the generic
+ SPMI controller binding requirements for child nodes.
+
+properties:
+ $nodename:
+ pattern: "^qcom,spmi@.*"
+
+ compatible:
+ const: qcom,spmi-pmic-arb
+
+ reg-names:
+ minItems: 3
+ maxItems: 5
+ items:
+ - const: core
+ - const: intr
+ - const: cnfg
+ - const: chnls
+ - const: obsrvr
+
+ reg:
+ minItems: 3
+ maxItems: 5
+ description: |
+ Specifies base physical address and size of the registers in SPMI PMIC
+ Arbiter HW module, with the following order.
+ - SPMI PMIC arbiter core registers (core)
+ - SPMI PMIC arbiter interrupt controller registers (intr)
+ - SPMI PMIC arbiter configuration registers (cnfg)
+ - SPMI PMIC arbiter tx-channel per virtual slave registers (chnls)
+ - SPMI PMIC arbiter rx-channel per virtual slave registers (obsrvr).
+ Register for "chnls" and "obsrvr" are only applicable for PMIC arbiter
+ with HW version greater than V2.
+
+ "#address-cells":
+ const: 2
+
+ "#size-cells":
+ const: 0
+
+ interrupts:
+ description: The summary interrupt for the PMIC Arb controller.
+ maxItems: 1
+
+ interrupt-names:
+ maxItems: 1
+ const: periph_irq
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 4
+ description: |
+ Specifies the number of cells needed to encode any interrupt source.
+ The 1st cell is the slave ID for the requested interrupt, its valid
+ range is [0-15].
+ The 2nd cell is the peripheral ID for requested interrupt, its valid
+ range is [0-255].
+ The 3rd cell is the requested peripheral interrupt, its valid range
+ is [0-7].
+ The 4th cell is interrupt flags indicating level-sense information,
+ as defined in dt-bindings/interrupt-controller/irq.h
+
+ qcom,ee:
+ description: the active Execution Environment identifier
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3, 4, 5]
+
+ qcom,channel:
+ description: which of the PMIC Arbiter provided channels to use for accesses
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [0, 1, 2, 3, 4, 5]
+
+required:
+ - compatible
+ - reg-names
+ - reg
+ - "#address-cells"
+ - "#size-cells"
+ - qcom,ee
+ - qcom,channel
+
+additionalProperties: false
+
+examples:
+ - |
+ qcom,spmi@...cf000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg-names = "core", "intr", "cnfg";
+ reg = <0xfc4cf000 0x1000>,
+ <0xfc4cb000 0x1000>,
+ <0xfc4ca000 0x1000>;
+ interrupt-names = "periph_irq";
+ interrupts = <0 190 0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+
+ #address-cells = <2>;
+ #size-cells = <0>;
+ };
--
2.7.4
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