linux-kernel - Re: [PATCH] PCI: Marvell: Update PCIe fixup

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Date:   Tue, 2 Nov 2021 16:13:34 +0100
From:   Pali Rohár <pali@...nel.org>
To:     Thomas Bogendoerfer <tsbogend@...ha.franken.de>
Cc:     Russell King <linux@...linux.org.uk>, Andrew Lunn <andrew@...n.ch>,
        Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>,
        Gregory Clement <gregory.clement@...tlin.com>,
        Jason Gunthorpe <jgg@...dia.com>,
        linux-arm-kernel@...ts.infradead.org, linux-mips@...r.kernel.org,
        linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] PCI: Marvell: Update PCIe fixup

On Tuesday 02 November 2021 16:02:01 Thomas Bogendoerfer wrote:
> On Tue, Nov 02, 2021 at 11:00:34AM +0100, Pali Rohár wrote:
> > > > But I do not have this hardware to verify it.
> > > 
> > > I still have a few Cobalt systems here.
> > 
> > Perfect! It would help if you could provide 'lspci -nn -vv' output from
> > that system. In case you have very old version of lspci on that system
> > you could try to run it with '-xxxx' (or '-xxx') which prints hexdump
> > and I can parse it with local lspci.
> 
> not sure, if you still needed:
> 
> root@...2:~# lspci -nn -vv
> 00:00.0 Host bridge [0600]: Marvell Technology Group Ltd. Device [11ab:4146] (rev 11)
> 	Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
> 	Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ >SERR- <PERR+ INTx-
> 	Latency: 64, Cache Line Size: 32 bytes
> 	Interrupt: pin A routed to IRQ 0
> 	Region 1: Memory at 08000000 (32-bit, non-prefetchable) [size=128M]
> 	Region 2: Memory at 1c000000 (32-bit, non-prefetchable) [size=32M]
> 	Region 3: Memory at 1f000000 (32-bit, non-prefetchable) [size=16M]
> 	Region 4: Memory at 14000000 (32-bit, non-prefetchable) [size=4K]
> 	Region 5: I/O ports at 4000000 [disabled] [size=4K]
> 
> 
> root@...2:~# lspci -xxxx
> 00:00.0 Host bridge: Marvell Technology Group Ltd. Device 4146 (rev 11)
> 00: ab 11 46 41 06 00 80 a2 11 00 80 05 08 40 00 00

                                 ^^ ^^ ^^
                           Here is class code

So it confirms that PCI Class code is 0580 which is Memory Controller.
And not Host Bridge as it should be.

If I put this hexdump into dump.txt and run 'lspci -F dump.txt -nn' then I see:
00:00.0 Memory controller [0580]: Marvell Technology Group Ltd. Device [11ab:4146] (rev 11)

In your output above is "Host bridge" which means that quirk was applied:
00:00.0 Host bridge [0600]: Marvell Technology Group Ltd. Device [11ab:4146] (rev 11)

(I guess in 'lspci -nn -vv -b' should be Memory controller as lspci with
'-b' should not see that quirk change)

> 10: 00 00 00 00 00 00 00 08 00 00 00 1c 00 00 00 1f
> 20: 00 00 00 14 01 00 00 14 00 00 00 00 00 00 00 00
> 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00
> 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
> 
> Thomas.
> 
> -- 
> Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
> good idea.                                                [ RFC1925, 2.3 ]