lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Wed, 3 Nov 2021 14:49:07 +0000 (GMT)
From:   "Maciej W. Rozycki" <macro@...am.me.uk>
To:     Pali Rohár <pali@...nel.org>
cc:     Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
        Russell King <linux@...linux.org.uk>,
        Andrew Lunn <andrew@...n.ch>,
        Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>,
        Gregory Clement <gregory.clement@...tlin.com>,
        Jason Gunthorpe <jgg@...dia.com>,
        Marek Behún <kabel@...nel.org>,
        linux-arm-kernel@...ts.infradead.org, linux-mips@...r.kernel.org,
        linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] PCI: Marvell: Update PCIe fixup

On Tue, 2 Nov 2021, Pali Rohár wrote:

> Hello Maciej! Thank you very much for the explanation!

 You are welcome!

> I'm surprised that Marvell copied this 20 years old MIPS Galileo PCI
> logic into followup ARM SoC PCIe IPs (and later also into recent ARM64
> A3720 SoC PCIe IP), removed configuration of PCI class code via
> strapping pins and let default PCI class code value to Memory device,
> even also when PCIe controller is running in Root Complex mode. And so
> correction can be done only from "CPU bus".

 Still the bootstrap firmware (say U-boot, as I can see it mentioned in 
your reference) can write the correct value to the class code register.  
Or can it?

 I guess you can try it and report your findings back.  You can poke at 
PCI/e registers directly from U-boot (`pci write.w', etc.) as with any 
reasonable firmware monitor, no need to write code; I guess you probably 
know that already.

 I have no such hardware and I have no incentive to chase documentation 
for it even if public copies are available for the affected devices.  
Also you say it's IP rather than actual discrete chips as it used to be 
with the Galileo system controllers, so it could be up to the customer to 
get the IP wired/configured correctly.

> Maciej, if I had known that you have this kind of information I would
> have written you year ago :-)

 Well, I have all kinds of information.

  Maciej

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ