linux-kernel - [PATCH] PCI: mediatek: Delay 100ms to wait power and clock to become stable

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Message-ID: <20211104062144.31453-1-qizhong.cheng@mediatek.com>
Date:   Thu, 4 Nov 2021 14:21:44 +0800
From:   qizhong cheng <qizhong.cheng@...iatek.com>
To:     Ryder Lee <ryder.lee@...iatek.com>,
        Jianjun Wang <jianjun.wang@...iatek.com>,
        Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        Krzysztof Wilczyiński <kw@...ux.com>,
        Bjorn Helgaas <bhelgaas@...gle.com>
CC:     <linux-pci@...r.kernel.org>, <linux-mediatek@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        Chuanjia Liu <chuanjia.liu@...iatek.com>,
        Jiey Yang <ot_jiey.yang@...iatek.com>,
        qizhong cheng <qizhong.cheng@...iatek.com>
Subject: [PATCH] PCI: mediatek: Delay 100ms to wait power and clock to become stable

Described in PCIe CEM specification setctions 2.2 (PERST# Signal) and
2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
be delayed 100ms (TPVPERL) for the power and clock to become stable.

Signed-off-by: qizhong cheng <qizhong.cheng@...iatek.com>
---
 drivers/pci/controller/pcie-mediatek.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
index 2f3f974977a3..b32acbac8084 100644
--- a/drivers/pci/controller/pcie-mediatek.c
+++ b/drivers/pci/controller/pcie-mediatek.c
@@ -702,6 +702,14 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
 	 */
 	writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
 
+	/*
+	 * Described in PCIe CEM specification setctions 2.2 (PERST# Signal)
+	 * and 2.2.1 (Initial Power-Up (G3 to S0)).
+	 * The deassertion of PERST# should be delayed 100ms (TPVPERL)
+	 * for the power and clock to become stable.
+	 */
+	msleep(100);
+
 	/* De-assert PHY, PE, PIPE, MAC and configuration reset	*/
 	val = readl(port->base + PCIE_RST_CTRL);
 	val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
-- 
2.25.1