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Message-Id: <20211106183802.893285-3-aford173@gmail.com>
Date: Sat, 6 Nov 2021 13:37:58 -0500
From: Adam Ford <aford173@...il.com>
To: linux-media@...r.kernel.org
Cc: tharvey@...eworks.com, frieder.schrempf@...tron.de,
marek.vasut@...il.com, jagan@...rulasolutions.com,
aford@...conembedded.com, cstevens@...conembedded.com,
Adam Ford <aford173@...il.com>,
Ezequiel Garcia <ezequiel@...guardiasur.com.ar>,
Philipp Zabel <p.zabel@...gutronix.de>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>,
NXP Linux Team <linux-imx@....com>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Heiko Stuebner <heiko@...ech.de>,
Lucas Stach <l.stach@...gutronix.de>,
Joakim Zhang <qiangqing.zhang@....com>,
Krzysztof Kozlowski <krzk@...nel.org>,
Peng Fan <peng.fan@....com>, Alice Guo <alice.guo@....com>,
linux-rockchip@...ts.infradead.org (open list:HANTRO VPU CODEC DRIVER),
devicetree@...r.kernel.org (open list:OPEN FIRMWARE AND FLATTENED
DEVICE TREE BINDINGS),
linux-arm-kernel@...ts.infradead.org (moderated list:ARM/FREESCALE IMX
/ MXC ARM ARCHITECTURE), linux-kernel@...r.kernel.org (open list),
linux-staging@...ts.linux.dev (open list:STAGING SUBSYSTEM)
Subject: [RFC 2/5] arm64: dts: imx8mm: Enable VPU-G1 and VPU-G2
Enable two hardware Hantro decoders called G1 and G2.
Signed-off-by: Adam Ford <aford173@...il.com>
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 41 +++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 1f69c14d953f..725c3113831e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1248,6 +1248,47 @@ gpu_2d: gpu@...08000 {
power-domains = <&pgc_gpu>;
};
+ vpu_g1: video-codec@...00000 {
+ compatible = "nxp,imx8mm-vpu";
+ reg = <0x38300000 0x10000>;
+ reg-names = "g1";
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "g1";
+ clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>,
+ <&clk IMX8MM_CLK_VPU_DEC_ROOT>;
+ clock-names = "g1", "bus";
+ assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>,
+ <&clk IMX8MM_CLK_VPU_BUS>,
+ <&clk IMX8MM_VPU_PLL_BYPASS>;
+ assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>,
+ <&clk IMX8MM_SYS_PLL1_800M>,
+ <&clk IMX8MM_VPU_PLL>;
+ assigned-clock-rates = <600000000>,
+ <800000000>,
+ <0>;
+ power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1>;
+ };
+
+ vpu_g2: video-codec@...10000 {
+ compatible = "nxp,imx8mm-vpu-g2";
+ reg = <0x38310000 0x10000>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "g2";
+ clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>,
+ <&clk IMX8MM_CLK_VPU_DEC_ROOT>;
+ clock-names = "g2", "bus";
+ assigned-clocks = <&clk IMX8MM_CLK_VPU_G2>,
+ <&clk IMX8MM_CLK_VPU_BUS>,
+ <&clk IMX8MM_VPU_PLL_BYPASS>;
+ assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>,
+ <&clk IMX8MM_SYS_PLL1_800M>,
+ <&clk IMX8MM_VPU_PLL>;
+ assigned-clock-rates = <600000000>,
+ <800000000>,
+ <0>;
+ power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2>;
+ };
+
vpu_blk_ctrl: blk-ctrl@...30000 {
compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";
reg = <0x38330000 0x100>;
--
2.32.0
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