linux-kernel - Re: [PATCH v3 11/11] arm64: dts: Add Pensando Elba SoC support

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Date:   Mon, 8 Nov 2021 10:25:52 +0000
From:   Mark Rutland <mark.rutland@....com>
To:     Brad Larson <brad@...sando.io>
Cc:     Linux ARM <linux-arm-kernel@...ts.infradead.org>,
        Arnd Bergmann <arnd@...db.de>,
        Linus Walleij <linus.walleij@...aro.org>,
        Bartosz Golaszewski <bgolaszewski@...libre.com>,
        Mark Brown <broonie@...nel.org>,
        Serge Semin <fancer.lancer@...il.com>,
        Adrian Hunter <adrian.hunter@...el.com>,
        Ulf Hansson <ulf.hansson@...aro.org>,
        Olof Johansson <olof@...om.net>,
        "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
        linux-spi <linux-spi@...r.kernel.org>,
        linux-mmc <linux-mmc@...r.kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v3 11/11] arm64: dts: Add Pensando Elba SoC support

On Thu, Nov 04, 2021 at 03:53:13PM -0700, Brad Larson wrote:
> On Mon, Oct 25, 2021 at 2:17 AM Mark Rutland <mark.rutland@....com> wrote:
> > On Sun, Oct 24, 2021 at 06:51:56PM -0700, Brad Larson wrote:
> > > +     timer {
> > > +             compatible = "arm,armv8-timer";
> > > +             interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
> > > +                                     IRQ_TYPE_LEVEL_LOW)>,
> > > +                          <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
> > > +                                     IRQ_TYPE_LEVEL_LOW)>,
> > > +                          <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
> > > +                                     IRQ_TYPE_LEVEL_LOW)>,
> > > +                          <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
> > > +                                     IRQ_TYPE_LEVEL_LOW)>;
> > > +     };
> >
> > The GIC_CPU_MASK_SIMPLE() stuff is meant for GICv2, but as below you
> > have GICv3, where this is not valid, so this should go.
> >
> > Also, beware that GIC_CPU_MASK_SIMPLE(1) means a single CPU, which
> > doesn't mak sense for the 16 CPUs you have.
> >
> 
> Thanks for pointing this out.  Elba SoC is a GICv3 implementation and looking
> at other device tree files we should be using this:
> 
>         timer {
>                 compatible = "arm,armv8-timer";
>                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(16) |
>                                         IRQ_TYPE_LEVEL_LOW)>,
>                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(16) |
>                                         IRQ_TYPE_LEVEL_LOW)>,
>                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(16) |
>                                         IRQ_TYPE_LEVEL_LOW)>,
>                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(16) |
>                                         IRQ_TYPE_LEVEL_LOW)>;
>         };

No; as above, you should *not* use GIC_CPU_MASK_SIMPLE() at all for GICv3. i.e.

>         timer {
>                 compatible = "arm,armv8-timer";
>                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
>                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
>                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
>                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
>         };

Please see the GICv3 binding documentation:

  Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml

... and note that it does not have the cpumask field as use by the binding for
prior generations of GIC:

  Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml


If you've seen other dts files using GIC_CPU_MASK_SIMPLE() with GICv3, those
are incorrect, and need to be fixed.

Thanks,
Mark.