linux-kernel - Question: SMMUv3 PMU event aliasing

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [thread-next>] [day] [month] [year] [list]

Date:   Mon, 8 Nov 2021 20:19:41 +0800
From:   Leo Yan <leo.yan@...aro.org>
To:     John Garry <john.garry@...wei.com>,
        linux-perf-users@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Question: SMMUv3 PMU event aliasing

Hi John,

[ + mailing list ]

I'd like to confirm the latest upstream status for SMMUv3 PMU event
aliasing.

I see the patch set v6 of "perf pmu-events: Support event aliasing for
system PMUs" [1] has been landed on the mainline kernel, and as an
example, imx8mm DDR PMU has been supported as system PMU [2].

On the other hand, I can see patch set 5 contains the SMMUv3 PMU event
aliasing with patch "perf vendor events arm64: Add Architected events
smmuv3-pmcg.json" [3], but this patch was left out in patch set 6 and
it's never landed on the mainline kernel.

Could you share current status (or plan) for upstreaming SMMUv3 PMU
event alias?  Or if there have any block issue to prevent merging the
changes in the mainline kernel?

Thanks for your help!

Leo

[1] https://lore.kernel.org/lkml/1607080216-36968-1-git-send-email-john.garry@huawei.com/
[2] pmu-events/arch/arm64/freescale/imx8mm/sys/ddrc.json
[3] https://lore.kernel.org/lkml/1604666153-4187-6-git-send-email-john.garry@huawei.com/