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Message-ID: <20211108150554.4457-10-conor.dooley@microchip.com>
Date: Mon, 8 Nov 2021 15:05:50 +0000
From: <conor.dooley@...rochip.com>
To: <linus.walleij@...aro.org>, <bgolaszewski@...libre.com>,
<robh+dt@...nel.org>, <jassisinghbrar@...il.com>,
<paul.walmsley@...ive.com>, <palmer@...belt.com>,
<aou@...s.berkeley.edu>, <a.zummo@...ertech.it>,
<alexandre.belloni@...tlin.com>, <broonie@...nel.org>,
<gregkh@...uxfoundation.org>, <lewis.hanly@...rochip.com>,
<conor.dooley@...rochip.com>, <daire.mcnamara@...rochip.com>,
<atish.patra@....com>, <ivan.griffin@...rochip.com>,
<linux-gpio@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-i2c@...r.kernel.org>,
<linux-riscv@...ts.infradead.org>, <linux-crypto@...r.kernel.org>,
<linux-rtc@...r.kernel.org>, <linux-spi@...r.kernel.org>,
<linux-usb@...r.kernel.org>
CC: <krzysztof.kozlowski@...onical.com>, <geert@...ux-m68k.org>,
<bin.meng@...driver.com>
Subject: [PATCH 09/13] dt-bindings: gpio: add bindings for microchip mpfs gpio
From: Conor Dooley <conor.dooley@...rochip.com>
Add device tree bindings for the gpio controller on
the Microchip PolarFire SoC.
Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
---
.../bindings/gpio/microchip,mpfs-gpio.yaml | 108 ++++++++++++++++++
1 file changed, 108 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
diff --git a/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
new file mode 100644
index 000000000000..067019ddc1f7
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
@@ -0,0 +1,108 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/microchip,mpfs-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip MPFS GPIO Controller Device Tree Bindings
+
+maintainers:
+ - Conor Dooley <conor.dooley@...rochip.com>
+
+description: |
+ This GPIO controller is found on the Microchip PolarFire SoC.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - microchip,mpfs-gpio
+ - microsemi,ms-pf-mss-gpio
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description:
+ Interrupt mapping, one per GPIO. Maximum 32 GPIOs.
+ minItems: 1
+ maxItems: 32
+
+ interrupt-controller: true
+
+ clocks:
+ maxItems: 1
+
+ "#gpio-cells":
+ const: 2
+
+ ngpios:
+ description:
+ The number of GPIOs available.
+ minimum: 1
+ maximum: 32
+ default: 32
+
+ gpio-controller: true
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - "#interrupt-cells"
+ - "#gpio-cells"
+ - gpio-controller
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include "dt-bindings/clock/microchip,mpfs-clock.h"
+ #include "dt-bindings/interrupt-controller/microchip,mpfs-plic.h"
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ gpio2: gpio@...22000 {
+ compatible = "microchip,mpfs-gpio";
+ reg = <0x0 0x20122000 0x0 0x1000>;
+ clocks = <&clkcfg CLK_GPIO2>;
+ interrupt-parent = <&plic>;
+ interrupts = <PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT
+ PLIC_INT_GPIO2_NON_DIRECT>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+ };
+...
--
2.33.1
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