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Message-Id: <BF6CBFFA-E8AA-4CCE-A587-4D5D647DEC64@goldelico.com>
Date: Tue, 9 Nov 2021 21:19:17 +0100
From: "H. Nikolaus Schaller" <hns@...delico.com>
To: Paul Cercueil <paul@...pouillou.net>
Cc: Paul Boddie <paul@...die.org.uk>, Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Kees Cook <keescook@...omium.org>,
"Eric W. Biederman" <ebiederm@...ssion.com>,
Miquel Raynal <miquel.raynal@...tlin.com>,
David Airlie <airlied@...ux.ie>,
Daniel Vetter <daniel@...ll.ch>,
Neil Armstrong <narmstrong@...libre.com>,
Robert Foss <robert.foss@...aro.org>,
Laurent Pinchart <Laurent.pinchart@...asonboard.com>,
Jernej Skrabec <jernej.skrabec@...il.com>,
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Sam Ravnborg <sam@...nborg.org>,
Maxime Ripard <maxime@...no.tech>,
Hans Verkuil <hverkuil-cisco@...all.nl>,
Liam Girdwood <lgirdwood@...il.com>,
Mark Brown <broonie@...nel.org>,
OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
<devicetree@...r.kernel.org>,
linux-mips <linux-mips@...r.kernel.org>,
linux-kernel <linux-kernel@...r.kernel.org>,
Discussions about the Letux Kernel
<letux-kernel@...nphoenux.org>, Jon as Karlman <jonas@...boo.se>,
dri-devel <dri-devel@...ts.freedesktop.org>
Subject: Re: [PATCH v5 5/7] MIPS: DTS: jz4780: Account for Synopsys HDMI
driver and LCD controllers
Hi Paul,
> Am 07.11.2021 um 20:05 schrieb Paul Cercueil <paul@...pouillou.net>:
>
>> 6. Therefore I think it *may* work overclocked with 48MHz
>> but is not guaranteed or reliable above 27 MHz.
>> So everything is ok here.
>
> One thing though - the "assigned-clocks" and "assigned-clock-rates", while it works here, should be moved to the CGU node, to respect the YAML schemas.
Trying to do this seems to break boot.
I can boot up to
[ 8.312926] dw-hdmi-ingenic 10180000.hdmi: registered DesignWare HDMI I2C bus driver
and
[ 11.366899] [drm] Initialized ingenic-drm 1.1.0 20200716 for 13050000.lcdc0 on minor 0
but then the boot process becomes slow and hangs. Last sign of activity is
[ 19.347659] hub 1-0:1.0: USB hub found
[ 19.353478] hub 1-0:1.0: 1 port detected
[ 32.321760] wlan0_power: disabling
What I did was to just move
assigned-clocks = <&cgu JZ4780_CLK_HDMI>;
assigned-clock-rates = <27000000>;
from
hdmi: hdmi@...80000 {
to
cgu: jz4780-cgu@...00000 {
Does this mean the clock is assigned too early or too late?
Do you have any suggestions since I don't know the details of CGU.
BR and thanks,
Nikolaus
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