linux-kernel - Re: [PATCH 04/13] dt-bindings: riscv: update microchip polarfire binds

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <CAMuHMdUs7UnADr2SfHBD4sGs3_giR0cmXnz=6qa4iAP1reDtgA@mail.gmail.com>
Date:   Tue, 9 Nov 2021 14:04:45 +0100
From:   Geert Uytterhoeven <geert@...ux-m68k.org>
To:     Conor Dooley <Conor.Dooley@...rochip.com>
Cc:     Linus Walleij <linus.walleij@...aro.org>,
        Bartosz Golaszewski <bgolaszewski@...libre.com>,
        Rob Herring <robh+dt@...nel.org>,
        Jassi Brar <jassisinghbrar@...il.com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        Palmer Dabbelt <palmer@...belt.com>,
        Albert Ou <aou@...s.berkeley.edu>,
        Alessandro Zummo <a.zummo@...ertech.it>,
        Alexandre Belloni <alexandre.belloni@...tlin.com>,
        Mark Brown <broonie@...nel.org>,
        Greg KH <gregkh@...uxfoundation.org>,
        Lewis Hanly <Lewis.Hanly@...rochip.com>,
        Daire.McNamara@...rochip.com, Atish Patra <atish.patra@....com>,
        Ivan.Griffin@...rochip.com,
        "open list:GPIO SUBSYSTEM" <linux-gpio@...r.kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Linux I2C <linux-i2c@...r.kernel.org>,
        linux-riscv <linux-riscv@...ts.infradead.org>,
        Linux Crypto Mailing List <linux-crypto@...r.kernel.org>,
        linux-rtc@...r.kernel.org, linux-spi <linux-spi@...r.kernel.org>,
        USB list <linux-usb@...r.kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>,
        Bin Meng <bin.meng@...driver.com>
Subject: Re: [PATCH 04/13] dt-bindings: riscv: update microchip polarfire binds

Hi Conor,

On Tue, Nov 9, 2021 at 1:08 PM <Conor.Dooley@...rochip.com> wrote:
> On 09/11/2021 08:34, Geert Uytterhoeven wrote:
> > On Mon, Nov 8, 2021 at 4:06 PM <conor.dooley@...rochip.com> wrote:
> >> From: Conor Dooley <conor.dooley@...rochip.com>
> >>
> >> Add mpfs-soc to clear undocumented binding warning
> >>
> >> Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>

> >> --- a/Documentation/devicetree/bindings/riscv/microchip.yaml
> >> +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml
> >> @@ -21,6 +21,7 @@ properties:
> >>         - enum:
> >>             - microchip,mpfs-icicle-kit
> >>         - const: microchip,mpfs
> >> +      - const: microchip,mpfs-soc
> >
> > Doesn't the "s" in "mpfs" already stand for "soc"?
> not wrong, but using mpf-soc would be confusing since "mpf" is the part
> name for the non soc fpga. is it fine to just reuse "mpfs" for the dtsi
> overall compatible and for the soc subsection?

I really meant: what is the difference between "microchip,mpfs" and
"microchip,mpfs-soc"? Can't you just use the former?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds