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Message-Id: <1636530670-6995-2-git-send-email-hammer.hsieh@sunplus.com>
Date: Wed, 10 Nov 2021 15:51:09 +0800
From: Hammer Hsieh <hammerh0314@...il.com>
To: gregkh@...uxfoundation.org, robh+dt@...nel.org,
linux-serial@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, jirislaby@...nel.org,
p.zabel@...gutronix.de
Cc: tony.huang@...plus.com, wells.lu@...plus.com,
Hammer Hsieh <hammer.hsieh@...plus.com>
Subject: [PATCH v2 1/2] dt-bindings:serial:Add bindings doc for Sunplus SoC UART Driver
Add bindings doc for Sunplus SoC UART Driver
Signed-off-by: Hammer Hsieh <hammer.hsieh@...plus.com>
---
Changes in v2:
- Addressed all comments from Mr. Rob Herring.
.../bindings/serial/sunplus,sp7021-uart.yaml | 157 +++++++++++++++++++++
MAINTAINERS | 5 +
2 files changed, 162 insertions(+)
create mode 100644 Documentation/devicetree/bindings/serial/sunplus,sp7021-uart.yaml
diff --git a/Documentation/devicetree/bindings/serial/sunplus,sp7021-uart.yaml b/Documentation/devicetree/bindings/serial/sunplus,sp7021-uart.yaml
new file mode 100644
index 0000000..3f46f3e
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/sunplus,sp7021-uart.yaml
@@ -0,0 +1,157 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) Sunplus Co., Ltd. 2021
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/serial/sunplus,sp7021-uart.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Sunplus SoC SP7021 UART Controller Device Tree Bindings
+
+maintainers:
+ - Tony Huang <tony.huang@...plus.com>
+ - Hammer Hsieh <hammer.hsieh@...plus.com>
+ - Wells Lu <wells.lu@...plus.com>
+
+allOf:
+ - $ref: serial.yaml#
+
+properties:
+ compatible:
+ const: sunplus,sp7021-uart
+
+ reg:
+ minItems: 1
+ maxItems: 2
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ oneOf:
+ - items:
+ - const: UADMA
+ - pattern: '^PERI[0-1]$'
+ - items:
+ - const: HWUA
+ - pattern: '^PERI[0-1]$'
+
+ resets:
+ maxItems: 1
+
+ which-uart:
+ description:
+ UA1-4 support DMA mode, UA0 support PIO mode only.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 1, 2, 3, 4]
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - resets
+
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - sunplus,sp7021-uart-rxdma
+ - sunplus,sp7021-uart-txdma
+then:
+ required:
+ - clock-names
+ - which-uart
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial10 = &uartdmarx0;
+ serial20 = &uartdmatx0;
+ serial11 = &uartdmarx1;
+ serial21 = &uartdmatx1;
+ };
+
+ // UART0 PIO mode only
+ uart0: serial@...00900 {
+ compatible = "sunplus,sp7021-uart";
+ reg = <0x9c000900 0x80>;
+ interrupt-parent = <&intc>;
+ interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkc 0x28>;
+ resets = <&rstc 0x18>;
+ };
+
+ // UART1 PIO mode
+ uart1: serial@...00980 {
+ compatible = "sunplus,sp7021-uart";
+ reg = <0x9c000980 0x80>;
+ interrupt-parent = <&intc>;
+ interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkc 0x29>;
+ resets = <&rstc 0x19>;
+ };
+
+ // UART1 DMA mode for RX
+ uartdmarx0: serial@...08980 {
+ compatible = "sunplus,sp7021-uart-rxdma";
+ reg = <0x9c008980 0x40>;
+ interrupt-parent = <&intc>;
+ interrupts = <138 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkc 0x2f>, <&clkc 0x1b>;
+ clock-names = "UADMA", "PERI0";
+ resets = <&rstc 0x1f>;
+ which-uart = <1>;
+ };
+
+ // UART1 DMA mode for TX
+ uartdmatx0: serial@...08a00 {
+ compatible = "sunplus,sp7021-uart-txdma";
+ reg = <0x9c008a00 0x40>, <0x9c008880 0x80>;
+ clocks = <&clkc 0x2d>, <&clkc 0x1b>;
+ clock-names = "HWUA", "PERI0";
+ resets = <&rstc 0x1d>;
+ which-uart = <1>;
+ };
+
+ // UART2 PIO mode
+ uart2: serial@...00800 {
+ compatible = "sunplus,sp7021-uart";
+ reg = <0x9c000800 0x80>;
+ interrupt-parent = <&intc>;
+ interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkc 0x2a>;
+ resets = <&rstc 0x1a>;
+ };
+
+ // UART2 DMA mode for RX
+ uartdmarx1: serial@...089c0 {
+ compatible = "sunplus,sp7021-uart-rxdma";
+ reg = <0x9c0089c0 0x40>;
+ interrupt-parent = <&intc>;
+ interrupts = <139 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clkc 0x2f>, <&clkc 0x1f>;
+ clock-names = "UADMA", "PERI1";
+ resets = <&rstc 0x1f>;
+ which-uart = <2>;
+ };
+
+ // UART2 DMA mode for TX
+ uartdmatx1: serial@...08a40 {
+ compatible = "sunplus,sp7021-uart-txdma";
+ reg = <0x9c008a40 0x40>, <0x9c008900 0x80>;
+ clocks = <&clkc 0x2d>, <&clkc 0x1f>;
+ clock-names = "HWUA", "PERI1";
+ resets = <&rstc 0x1d>;
+ which-uart = <2>;
+ };
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 3b79fd4..f2ee40c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17945,6 +17945,11 @@ L: netdev@...r.kernel.org
S: Maintained
F: drivers/net/ethernet/dlink/sundance.c
+SUNPLUS UART DRIVER
+M: Hammer Hsieh <hammer.hsieh@...plus.com>
+S: Maintained
+F: Documentation/devicetree/bindings/serial/sunplus,sp7021-uart.yaml
+
SUPERH
M: Yoshinori Sato <ysato@...rs.sourceforge.jp>
M: Rich Felker <dalias@...c.org>
--
2.7.4
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