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Message-ID: <6b065b43-e3a8-a3ff-d537-7cf70b153d22@microchip.com>
Date: Wed, 10 Nov 2021 15:07:11 +0000
From: <Conor.Dooley@...rochip.com>
To: <geert@...ux-m68k.org>
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Subject: Re: [PATCH 12/13] riscv: icicle-kit: update microchip icicle kit
device tree
On 10/11/2021 14:58, Geert Uytterhoeven wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Hi Conor,
>
>>>> plic: interrupt-controller@...0000 {
>>>> - #interrupt-cells = <1>;
>>>> - compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
>>>> + compatible = "sifive,plic-1.0.0";
>>>
>>> Why drop the first one again?
>> we felt it didnt make sense to have something that specifically
>> references the fu540 in the device tree for this board.
>
> That would be a revert of commit 73d3c44115514616 ("riscv: dts:
> microchip: add missing compatibles for clint and plic"), which you
> supplied an R-b tag for?
>
> Is this the same plic as in the FU540 SoC? Or do we need a new
> microchip,mpfs-plic compatible value?
>
yeah, ignore that. i confused this change (which is an accidental
clobber) with another sifive compatible that was dropped for not being
relevant. hardly makes sense to drop this one when i kept it for the
clint and cache controller!
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
>
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