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Message-Id: <20211112130627.3682795-6-thierry.reding@gmail.com>
Date: Fri, 12 Nov 2021 14:06:27 +0100
From: Thierry Reding <thierry.reding@...il.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>,
Rob Herring <robh+dt@...nel.org>
Cc: Thierry Reding <thierry.reding@...il.com>,
Jon Hunter <jonathanh@...dia.com>, linux-tegra@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: [PATCH 5/5] arm64: tegra: Hook up MMC and BPMP to memory controller
From: Thierry Reding <treding@...dia.com>
Use the interconnects property to hook up the MMC and BPMP to the memory
controller. This is needed to set the correct bus-level DMA mask, which
is a prerequisite for adding IOMMU support.
Signed-off-by: Thierry Reding <treding@...dia.com>
---
arch/arm64/boot/dts/nvidia/tegra234.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index 8893d110a0ae..07ab9137f681 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -157,6 +157,9 @@ mmc@...0000 {
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>;
resets = <&bpmp TEGRA234_RESET_SDMMC4>;
reset-names = "sdhci";
+ interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>,
+ <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>;
+ interconnect-names = "dma-mem", "write";
nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
@@ -289,6 +292,11 @@ bpmp: bpmp {
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
+ interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>,
+ <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>,
+ <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>,
+ <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>;
+ interconnect-names = "read", "write", "dma-mem", "dma-write";
bpmp_i2c: i2c {
compatible = "nvidia,tegra186-bpmp-i2c";
--
2.33.1
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