linux-kernel - Re: [PATCH] arm64: dts: k3-j721e: correct cache-sets info

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Date:   Fri, 12 Nov 2021 20:26:21 -0600
From:   Nishanth Menon <nm@...com>
To:     "Peng Fan (OSS)" <peng.fan@....nxp.com>
CC:     <robh+dt@...nel.org>, <vigneshr@...com>, <kristo@...nel.org>,
        <s-anna@...com>, <linux-arm-kernel@...ts.infradead.org>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        Peng Fan <peng.fan@....com>
Subject: Re: [PATCH] arm64: dts: k3-j721e: correct cache-sets info

On 14:31-20211112, Peng Fan (OSS) wrote:
> From: Peng Fan <peng.fan@....com>
> 
> A72 Cluster has 48KB Icache, 32KB Dcache and 1MB L2 Cache
>  - ICache is 3-way set-associative
>  - Dcache is 2-way set-associative
>  - Line size are 64bytes
> 
> So correct the cache-sets info.
> 
> Fixes: 2d87061e70dea ("arm64: dts: ti: Add Support for J721E SoC")
> Signed-off-by: Peng Fan <peng.fan@....com>
> ---
>  arch/arm64/boot/dts/ti/k3-j721e.dtsi | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
> index 214359e7288b..a5967ba139d7 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
> @@ -64,7 +64,7 @@ cpu0: cpu@0 {
>  			i-cache-sets = <256>;
>  			d-cache-size = <0x8000>;
>  			d-cache-line-size = <64>;
> -			d-cache-sets = <128>;
> +			d-cache-sets = <256>;
>  			next-level-cache = <&L2_0>;
>  		};
>  
> @@ -78,7 +78,7 @@ cpu1: cpu@1 {
>  			i-cache-sets = <256>;
>  			d-cache-size = <0x8000>;
>  			d-cache-line-size = <64>;
> -			d-cache-sets = <128>;
> +			d-cache-sets = <256>;
>  			next-level-cache = <&L2_0>;
>  		};
>  	};
> -- 
> 2.25.1
> 
Arrgh.. Thank you for fixing this.

Reviewed-by: Nishanth Menon <nm@...com>

I think J7200 also needs fixups. Will cross check and post additional
patches depending on the ones that need it.

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D