linux-kernel - [PATCH] arm64: dts: ti: k3-j7200: Fix the L2 cache sets

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Message-ID: <20211113043638.4358-1-nm@ti.com>
Date:   Fri, 12 Nov 2021 22:36:38 -0600
From:   Nishanth Menon <nm@...com>
To:     Rob Herring <robh+dt@...nel.org>, Tero Kristo <kristo@...nel.org>,
        Vignesh Raghavendra <vigneshr@...com>
CC:     <linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>, Nishanth Menon <nm@...com>,
        <linux-omap@...r.kernel.org>, Peng Fan <peng.fan@....com>
Subject: [PATCH] arm64: dts: ti: k3-j7200: Fix the L2 cache sets

A72's L2 cache[1] on J7200[2] is 1MB. A53's L2 is fixed line length of
64 bytes and 16-way set-associative cache structure.

1MB of L2 / 64 (line length) = 16384 ways
16384 ways / 16 = 1024 sets

Fix the l2 cache-sets.

[1] https://developer.arm.com/documentation/100095/0003/Level-2-Memory-System/About-the-L2-memory-system
[2] https://www.ti.com/lit/pdf/spruiu1

Fixes: d361ed88455f ("arm64: dts: ti: Add support for J7200 SoC")
Reported-by: Peng Fan <peng.fan@....com>
Signed-off-by: Nishanth Menon <nm@...com>
---
 arch/arm64/boot/dts/ti/k3-j7200.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
index 958587d3a33d..64fef4e67d76 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
@@ -86,7 +86,7 @@ L2_0: l2-cache0 {
 		cache-level = <2>;
 		cache-size = <0x100000>;
 		cache-line-size = <64>;
-		cache-sets = <2048>;
+		cache-sets = <1024>;
 		next-level-cache = <&msmc_l3>;
 	};
 
-- 
2.32.0