| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <167392de-8b5e-6877-94aa-66d9368e96a7@gmail.com>
Date: Sun, 14 Nov 2021 12:33:19 +0100
From: Johan Jonker <jbx6244@...il.com>
To: Yifeng Zhao <yifeng.zhao@...k-chips.com>, heiko@...ech.de,
robh+dt@...nel.org
Cc: devicetree@...r.kernel.org, vkoul@...nel.org,
michael.riesch@...fvision.net, linux-rockchip@...ts.infradead.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-phy@...ts.infradead.org, kishon@...com,
p.zabel@...gutronix.de, cl@...k-chips.com
Subject: Re: [PATCH v3 3/3] arm64: dts: rockchip: add naneng combo phy nodes
for rk3568
Hi Yifeng,
Add more compatible strings to:
Documentation/devicetree/bindings/mfd/syscon.yaml
Also add mfd maintainers and list to CC.
On 10/25/21 10:06 AM, Yifeng Zhao wrote:
> Add the core dt-node for the rk3568's naneng combo phys.
>
> Signed-off-by: Zhao <yifeng.zhao@...k-chips.com>
> ---
>
> Changes in v3:
> - Move pipe_phy_grf0 to rk3568.dtsi
>
> Changes in v2:
> - Move phy0 to rk3568.dtsi
>
> arch/arm64/boot/dts/rockchip/rk3568.dtsi | 21 +++++++++++
> arch/arm64/boot/dts/rockchip/rk356x.dtsi | 47 ++++++++++++++++++++++++
> 2 files changed, 68 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> index 2fd313a295f8..4db5d3c2a04e 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> @@ -8,6 +8,11 @@
> / {
> compatible = "rockchip,rk3568";
>
> + pipe_phy_grf0: syscon@...70000 {
> + compatible = "rockchip,pipe-phy-grf", "syscon";
Compatible strings are supposed to be SOC related.
compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
> + reg = <0x0 0xfdc70000 0x0 0x1000>;
> + };
> +
> qos_pcie3x1: qos@...90080 {
> compatible = "rockchip,rk3568-qos", "syscon";
> reg = <0x0 0xfe190080 0x0 0x20>;
> @@ -71,6 +76,22 @@
> queue0 {};
> };
> };
> +
> + combphy0_us: phy@...20000 {
> + compatible = "rockchip,rk3568-naneng-combphy";
> + reg = <0x0 0xfe820000 0x0 0x100>;
> + #phy-cells = <1>;
Dump things with "#" down the list above status.
> + clocks = <&pmucru CLK_PCIEPHY0_REF>, <&cru PCLK_PIPEPHY0>,
> + <&cru PCLK_PIPE>;
> + clock-names = "ref", "apb", "pipe";
> + assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
> + assigned-clock-rates = <100000000>;
> + resets = <&cru SRST_P_PIPEPHY0>, <&cru SRST_PIPEPHY0>;
> + reset-names = "combphy-apb", "combphy";
There are 2 resets. When the reset order does matter then use
devm_reset_control_array_get() to get the resets.
The use of reset-names is then not needed.
> + rockchip,pipe-grf = <&pipegrf>;
> + rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
> + status = "disabled";
> + };
> };
>
> &cpu0_opp_table {
> diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> index 46d9552f6028..4380580d061b 100644
> --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
> @@ -214,11 +214,26 @@
> };
> };
>
> + pipegrf: syscon@...50000 {
> + compatible = "rockchip,rk3568-pipegrf", "syscon";
compatible = "rockchip,rk3568-pipe-grf", "syscon";
> + reg = <0x0 0xfdc50000 0x0 0x1000>;
> + };
> +
> grf: syscon@...60000 {
> compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
> reg = <0x0 0xfdc60000 0x0 0x10000>;
> };
>
> + pipe_phy_grf1: syscon@...80000 {
> + compatible = "rockchip,pipe-phy-grf", "syscon";
Compatible strings are supposed to be SOC related.
compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
> + reg = <0x0 0xfdc80000 0x0 0x1000>;
> + };
> +
> + pipe_phy_grf2: syscon@...90000 {
> + compatible = "rockchip,pipe-phy-grf", "syscon";
Compatible strings are supposed to be SOC related.
compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
> + reg = <0x0 0xfdc90000 0x0 0x1000>;
> + };
> +
> pmucru: clock-controller@...00000 {
> compatible = "rockchip,rk3568-pmucru";
> reg = <0x0 0xfdd00000 0x0 0x1000>;
> @@ -1077,6 +1092,38 @@
> status = "disabled";
> };
>
> + combphy1_usq: phy@...30000 {
> + compatible = "rockchip,rk3568-naneng-combphy";
> + reg = <0x0 0xfe830000 0x0 0x100>;
> + #phy-cells = <1>;
dito
> + clocks = <&pmucru CLK_PCIEPHY1_REF>, <&cru PCLK_PIPEPHY1>,
> + <&cru PCLK_PIPE>;
> + clock-names = "ref", "apb", "pipe";
> + assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
> + assigned-clock-rates = <100000000>;
> + resets = <&cru SRST_P_PIPEPHY1>, <&cru SRST_PIPEPHY1>;
> + reset-names = "combphy-apb", "combphy";
dito
> + rockchip,pipe-grf = <&pipegrf>;
> + rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
> + status = "disabled";
> + };
> +
> + combphy2_psq: phy@...40000 {
> + compatible = "rockchip,rk3568-naneng-combphy";
> + reg = <0x0 0xfe840000 0x0 0x100>;
> + #phy-cells = <1>;
dito
> + clocks = <&pmucru CLK_PCIEPHY2_REF>, <&cru PCLK_PIPEPHY2>,
> + <&cru PCLK_PIPE>;
> + clock-names = "ref", "apb", "pipe";
> + assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
> + assigned-clock-rates = <100000000>;
> + resets = <&cru SRST_P_PIPEPHY2>, <&cru SRST_PIPEPHY2>;
> + reset-names = "combphy-apb", "combphy";
dito
> + rockchip,pipe-grf = <&pipegrf>;
> + rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
> + status = "disabled";
> + };
> +
> pinctrl: pinctrl {
> compatible = "rockchip,rk3568-pinctrl";
> rockchip,grf = <&grf>;
>
Powered by blists - more mailing lists