| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Mon, 15 Nov 2021 12:53:40 +0200
From: Jani Nikula <jani.nikula@...ux.intel.com>
To: Lyude Paul <lyude@...hat.com>, intel-gfx@...ts.freedesktop.org
Cc: Ville Syrjälä <ville.syrjala@...ux.intel.com>,
stable@...r.kernel.org,
Joonas Lahtinen <joonas.lahtinen@...ux.intel.com>,
Rodrigo Vivi <rodrigo.vivi@...el.com>,
Tvrtko Ursulin <tvrtko.ursulin@...ux.intel.com>,
David Airlie <airlied@...ux.ie>,
Daniel Vetter <daniel@...ll.ch>,
Imre Deak <imre.deak@...el.com>,
José Roberto de Souza
<jose.souza@...el.com>, Uma Shankar <uma.shankar@...el.com>,
Anshuman Gupta <anshuman.gupta@...el.com>,
Dave Airlie <airlied@...hat.com>,
Gwan-gyeong Mun <gwan-gyeong.mun@...el.com>,
Manasi Navare <manasi.d.navare@...el.com>,
Ankit Nautiyal <ankit.k.nautiyal@...el.com>,
"open list\:DRM DRIVERS" <dri-devel@...ts.freedesktop.org>,
open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] drm/i915/dp: Perform 30ms delay after source OUI write
On Fri, 12 Nov 2021, Lyude Paul <lyude@...hat.com> wrote:
> While working on supporting the Intel HDR backlight interface, I noticed
> that there's a couple of laptops that will very rarely manage to boot up
> without detecting Intel HDR backlight support - even though it's supported
> on the system. One example of such a laptop is the Lenovo P17 1st
> generation.
>
> Following some investigation Ville Syrjälä did through the docs they have
> available to them, they discovered that there's actually supposed to be a
> 30ms wait after writing the source OUI before we begin setting up the rest
> of the backlight interface.
>
> This seems to be correct, as adding this 30ms delay seems to have
> completely fixed the probing issues I was previously seeing. So - let's
> start performing a 30ms wait after writing the OUI, which we do in a manner
> similar to how we keep track of PPS delays (e.g. record the timestamp of
> the OUI write, and then wait for however many ms are left since that
> timestamp right before we interact with the backlight) in order to avoid
> waiting any longer then we need to. As well, this also avoids us performing
> this delay on systems where we don't end up using the HDR backlight
> interface.
Ugh. Thanks for digging into this.
The only thing that I dislike with the implementation is splitting the
implementation to two places. See how well we've managed to shove all of
the PPS waits inside intel_pps.c. Almost all of intel_dp->pps is managed
within intel_pps.c.
I think I'd actually add a intel_dp_wait_source_oui() or something in
intel_dp.c, so all of the details about source OUI and
intel_dp->last_oui_write access would be localized.
BR,
Jani.
>
> Signed-off-by: Lyude Paul <lyude@...hat.com>
> Fixes: 4a8d79901d5b ("drm/i915/dp: Enable Intel's HDR backlight interface (only SDR for now)")
> Cc: Ville Syrjälä <ville.syrjala@...ux.intel.com>
> Cc: <stable@...r.kernel.org> # v5.12+
> ---
> drivers/gpu/drm/i915/display/intel_display_types.h | 3 +++
> drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
> drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 11 +++++++++++
> 3 files changed, 17 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index ea1e8a6e10b0..b9c967837872 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1653,6 +1653,9 @@ struct intel_dp {
> struct intel_dp_pcon_frl frl;
>
> struct intel_psr psr;
> +
> + /* When we last wrote the OUI for eDP */
> + unsigned long last_oui_write;
> };
>
> enum lspcon_vendor {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 0a424bf69396..77d9a9390c1e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -29,6 +29,7 @@
> #include <linux/i2c.h>
> #include <linux/notifier.h>
> #include <linux/slab.h>
> +#include <linux/timekeeping.h>
> #include <linux/types.h>
>
> #include <asm/byteorder.h>
> @@ -2010,6 +2011,8 @@ intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful)
>
> if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0)
> drm_err(&i915->drm, "Failed to write source OUI\n");
> +
> + intel_dp->last_oui_write = jiffies;
> }
>
> /* If the device supports it, try to set the power state appropriately */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> index 569d17b4d00f..2c35b999ec2c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c
> @@ -96,6 +96,13 @@
> #define INTEL_EDP_BRIGHTNESS_OPTIMIZATION_1 0x359
>
> /* Intel EDP backlight callbacks */
> +static void
> +wait_for_oui(struct drm_i915_private *i915, struct intel_dp *intel_dp)
> +{
> + drm_dbg_kms(&i915->drm, "Performing OUI wait\n");
> + wait_remaining_ms_from_jiffies(intel_dp->last_oui_write, 30);
> +}
> +
> static bool
> intel_dp_aux_supports_hdr_backlight(struct intel_connector *connector)
> {
> @@ -106,6 +113,8 @@ intel_dp_aux_supports_hdr_backlight(struct intel_connector *connector)
> int ret;
> u8 tcon_cap[4];
>
> + wait_for_oui(i915, intel_dp);
> +
> ret = drm_dp_dpcd_read(aux, INTEL_EDP_HDR_TCON_CAP0, tcon_cap, sizeof(tcon_cap));
> if (ret != sizeof(tcon_cap))
> return false;
> @@ -204,6 +213,8 @@ intel_dp_aux_hdr_enable_backlight(const struct intel_crtc_state *crtc_state,
> int ret;
> u8 old_ctrl, ctrl;
>
> + wait_for_oui(i915, intel_dp);
> +
> ret = drm_dp_dpcd_readb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, &old_ctrl);
> if (ret != 1) {
> drm_err(&i915->drm, "Failed to read current backlight control mode: %d\n", ret);
--
Jani Nikula, Intel Open Source Graphics Center
Powered by blists - more mailing lists