[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <1637060508-30375-3-git-send-email-pmaliset@codeaurora.org>
Date: Tue, 16 Nov 2021 16:31:47 +0530
From: Prasad Malisetty <pmaliset@...eaurora.org>
To: swboyd@...omium.org, agross@...nel.org, bjorn.andersson@...aro.org,
devicetree@...r.kernel.org, linux-arm-msm@...r.kernel.org,
linux-kernel@...r.kernel.org, manivannan.sadhasivam@...aro.org,
robh+dt@...nel.org, mka@...omium.org, lorenzo.pieralisi@....com,
svarbanov@...sol.com, bhelgaas@...gle.com
Cc: Prasad Malisetty <pmaliset@...eaurora.org>
Subject: [PATCH v3 2/3] arm64: dts: qcom: sc7280: Add pcie clock support
Add pcie clock phandle for sc7280 SoC.
Signed-off-by: Prasad Malisetty <pmaliset@...eaurora.org>
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index cb94b87..3fb9338 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -574,7 +574,8 @@
reg = <0 0x00100000 0 0x1f0000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
- <0>, <0>, <0>, <0>, <0>, <0>;
+ <0>, <&pcie1_lane 0>,
+ <0>, <0>, <0>, <0>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
"pcie_0_pipe_clk", "pcie_1_pipe_clk",
"ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk",
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
Powered by blists - more mailing lists