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Message-ID: <20211116155413.164242-2-jonathanh@nvidia.com>
Date: Tue, 16 Nov 2021 15:54:13 +0000
From: Jon Hunter <jonathanh@...dia.com>
To: Rob Herring <robh+dt@...nel.org>,
Thierry Reding <thierry.reding@...il.com>,
Mikko Perttunen <mperttunen@...dia.com>
CC: <devicetree@...r.kernel.org>, <linux-tegra@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, Jon Hunter <jonathanh@...dia.com>
Subject: [PATCH V2 2/2] arm64: tegra: Add NVENC and NVJPG nodes for Tegra186 and Tegra194
Populate the device-tree nodes for NVENC and NVJPG Host1x engines on
Tegra186 and Tegra194.
Signed-off-by: Jon Hunter <jonathanh@...dia.com>
---
Changes since V1:
- None
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 30 +++++++++++++
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 54 ++++++++++++++++++++++++
2 files changed, 84 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 9ac4f0140700..f21cfcaab2a6 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -1538,6 +1538,21 @@ vic@...40000 {
iommus = <&smmu TEGRA186_SID_VIC>;
};
+ nvjpg@...80000 {
+ compatible = "nvidia,tegra186-nvjpg";
+ reg = <0x15380000 0x40000>;
+ clocks = <&bpmp TEGRA186_CLK_NVJPG>;
+ clock-names = "nvjpg";
+ resets = <&bpmp TEGRA186_RESET_NVJPG>;
+ reset-names = "nvjpg";
+
+ power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVJPG>;
+ interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA186_SID_NVJPG>;
+ };
+
dsib: dsi@...00000 {
compatible = "nvidia,tegra186-dsi";
reg = <0x15400000 0x10000>;
@@ -1569,6 +1584,21 @@ nvdec@...80000 {
iommus = <&smmu TEGRA186_SID_NVDEC>;
};
+ nvenc@...c0000 {
+ compatible = "nvidia,tegra186-nvenc";
+ reg = <0x154c0000 0x40000>;
+ clocks = <&bpmp TEGRA186_CLK_NVENC>;
+ clock-names = "nvenc";
+ resets = <&bpmp TEGRA186_RESET_NVENC>;
+ reset-names = "nvenc";
+
+ power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>;
+ interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>,
+ <&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA186_SID_NVENC>;
+ };
+
sor0: sor@...40000 {
compatible = "nvidia,tegra186-sor";
reg = <0x15540000 0x10000>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 1adf076526c8..9586af9a100b 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -1782,6 +1782,22 @@ vic@...40000 {
dma-coherent;
};
+ nvjpg@...80000 {
+ compatible = "nvidia,tegra194-nvjpg";
+ reg = <0x15380000 0x40000>;
+ clocks = <&bpmp TEGRA194_CLK_NVJPG>;
+ clock-names = "nvjpg";
+ resets = <&bpmp TEGRA194_RESET_NVJPG>;
+ reset-names = "nvjpg";
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVJPG>;
+ interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVJPGSRD &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVJPGSWR &emc>;
+ interconnect-names = "dma-mem", "write";
+ iommus = <&smmu TEGRA194_SID_NVJPG>;
+ dma-coherent;
+ };
+
nvdec@...80000 {
compatible = "nvidia,tegra194-nvdec";
reg = <0x15480000 0x00040000>;
@@ -1801,6 +1817,25 @@ nvdec@...80000 {
nvidia,host1x-class = <0xf0>;
};
+ nvenc@...c0000 {
+ compatible = "nvidia,tegra194-nvenc";
+ reg = <0x154c0000 0x40000>;
+ clocks = <&bpmp TEGRA194_CLK_NVENC>;
+ clock-names = "nvenc";
+ resets = <&bpmp TEGRA194_RESET_NVENC>;
+ reset-names = "nvenc";
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCA>;
+ interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVENCSRD1 &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVENCSWR &emc>;
+ interconnect-names = "dma-mem", "read-1", "write";
+ iommus = <&smmu TEGRA194_SID_NVENC>;
+ dma-coherent;
+
+ nvidia,host1x-class = <0x21>;
+ };
+
dpaux0: dpaux@...c0000 {
compatible = "nvidia,tegra194-dpaux";
reg = <0x155c0000 0x10000>;
@@ -1937,6 +1972,25 @@ i2c-bus {
};
};
+ nvenc@...80000 {
+ compatible = "nvidia,tegra194-nvenc";
+ reg = <0x15a80000 0x00040000>;
+ clocks = <&bpmp TEGRA194_CLK_NVENC1>;
+ clock-names = "nvenc";
+ resets = <&bpmp TEGRA194_RESET_NVENC1>;
+ reset-names = "nvenc";
+
+ power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVENCB>;
+ interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVENC1SRD1 &emc>,
+ <&mc TEGRA194_MEMORY_CLIENT_NVENC1SWR &emc>;
+ interconnect-names = "dma-mem", "read-1", "write";
+ iommus = <&smmu TEGRA194_SID_NVENC1>;
+ dma-coherent;
+
+ nvidia,host1x-class = <0x22>;
+ };
+
sor0: sor@...00000 {
compatible = "nvidia,tegra194-sor";
reg = <0x15b00000 0x40000>;
--
2.25.1
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