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Message-ID: <20211117052448.GE215087@roeck-us.net>
Date: Tue, 16 Nov 2021 21:24:48 -0800
From: Guenter Roeck <linux@...ck-us.net>
To: AceLan Kao <acelan.kao@...onical.com>
Cc: Wim Van Sebroeck <wim@...ux-watchdog.org>,
linux-watchdog@...r.kernel.org, linux-kernel@...r.kernel.org,
SophieHu <sophiehu@...on.com.tw>
Subject: Re: [PATCH] watchdog: f71808e_wdt: Add F81966 support
On Wed, Nov 17, 2021 at 10:40:52AM +0800, AceLan Kao wrote:
> From: AaeonIot <sophiehu@...on.com.tw>
>
> This adds watchdog support the Fintek F81966 Super I/O chip.
> Testing was done on the Aaeon SSE-OPTI
>
> Signed-off-by: AaeonIot <sophiehu@...on.com.tw>
> Signed-off-by: Chia-Lin Kao (AceLan) <acelan.kao@...onical.com>
Reviewed-by: Guenter Roeck <linux@...ck-us.net>
> ---
> drivers/watchdog/f71808e_wdt.c | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/watchdog/f71808e_wdt.c b/drivers/watchdog/f71808e_wdt.c
> index ee90c5f943f9..7f59c680de25 100644
> --- a/drivers/watchdog/f71808e_wdt.c
> +++ b/drivers/watchdog/f71808e_wdt.c
> @@ -49,6 +49,7 @@
> #define SIO_F81803_ID 0x1210 /* Chipset ID */
> #define SIO_F81865_ID 0x0704 /* Chipset ID */
> #define SIO_F81866_ID 0x1010 /* Chipset ID */
> +#define SIO_F81966_ID 0x1502 /* F81804 chipset ID, same for f81966 */
>
> #define F71808FG_REG_WDO_CONF 0xf0
> #define F71808FG_REG_WDT_CONF 0xf5
> @@ -105,7 +106,7 @@ MODULE_PARM_DESC(start_withtimeout, "Start watchdog timer on module load with"
> " given initial timeout. Zero (default) disables this feature.");
>
> enum chips { f71808fg, f71858fg, f71862fg, f71868, f71869, f71882fg, f71889fg,
> - f81803, f81865, f81866};
> + f81803, f81865, f81866, f81966};
>
> static const char * const fintek_wdt_names[] = {
> "f71808fg",
> @@ -118,6 +119,7 @@ static const char * const fintek_wdt_names[] = {
> "f81803",
> "f81865",
> "f81866",
> + "f81966"
> };
>
> /* Super-I/O Function prototypes */
> @@ -347,6 +349,7 @@ static int fintek_wdt_start(struct watchdog_device *wdd)
> break;
>
> case f81866:
> + case f81966:
> /*
> * GPIO1 Control Register when 27h BIT3:2 = 01 & BIT0 = 0.
> * The PIN 70(GPIO15/WDTRST) is controlled by 2Ch:
> @@ -373,7 +376,7 @@ static int fintek_wdt_start(struct watchdog_device *wdd)
> superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT);
> superio_set_bit(wd->sioaddr, SIO_REG_ENABLE, 0);
>
> - if (wd->type == f81865 || wd->type == f81866)
> + if (wd->type == f81865 || wd->type == f81866 || wd->type == f81966)
> superio_set_bit(wd->sioaddr, F81865_REG_WDO_CONF,
> F81865_FLAG_WDOUT_EN);
> else
> @@ -580,6 +583,9 @@ static int __init fintek_wdt_find(int sioaddr)
> case SIO_F81866_ID:
> type = f81866;
> break;
> + case SIO_F81966_ID:
> + type = f81966;
> + break;
> default:
> pr_info("Unrecognized Fintek device: %04x\n",
> (unsigned int)devid);
> --
> 2.25.1
>
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