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Message-Id: <20211117093734.17407-18-daniel.baluta@oss.nxp.com>
Date: Wed, 17 Nov 2021 11:37:30 +0200
From: Daniel Baluta <daniel.baluta@....nxp.com>
To: broonie@...nel.org, alsa-devel@...a-project.org
Cc: pierre-louis.bossart@...ux.intel.com, lgirdwood@...il.com,
daniel.baluta@....com, daniel.baluta@...il.com,
AjitKumar.Pandey@....com, Balakishore.pati@....com,
vsreddy@....com, Julian.Schroeder@....com,
vishnuvardhanrao.ravulapati@....com, linux-kernel@...r.kernel.org,
yc.hung@...iatek.com, linux-mediatek@...ts.infradead.org,
Péter Ujfalusi <peter.ujfalusi@...ux.intel.com>,
Ranjani Sridharan <ranjani.sridharan@...ux.intel.com>,
Kai Vehmanen <kai.vehmanen@...ux.intel.com>,
Guennadi Liakhovetski <guennadi.liakhovetski@...ux.intel.com>
Subject: [PATCH 17/21] ASoC: SOF: mediatek: Add fw loader and mt8195 dsp ops to load firmware
From: YC Hung <yc.hung@...iatek.com>
Add mt8195-loader module with ops callback to load and run firmware
on mt8195 platform.
Signed-off-by: YC Hung <yc.hung@...iatek.com>
Reviewed-by: Péter Ujfalusi <peter.ujfalusi@...ux.intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@...ux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@...ux.intel.com>
Reviewed-by: Kai Vehmanen <kai.vehmanen@...ux.intel.com>
Reviewed-by: Guennadi Liakhovetski <guennadi.liakhovetski@...ux.intel.com>
Reviewed-by: Daniel Baluta <daniel.baluta@....com>
Signed-off-by: Daniel Baluta <daniel.baluta@....com>
---
sound/soc/sof/mediatek/mt8195/Makefile | 2 +-
sound/soc/sof/mediatek/mt8195/mt8195-loader.c | 56 +++++++++++++++++++
sound/soc/sof/mediatek/mt8195/mt8195.c | 8 +++
sound/soc/sof/mediatek/mt8195/mt8195.h | 3 +
4 files changed, 68 insertions(+), 1 deletion(-)
create mode 100644 sound/soc/sof/mediatek/mt8195/mt8195-loader.c
diff --git a/sound/soc/sof/mediatek/mt8195/Makefile b/sound/soc/sof/mediatek/mt8195/Makefile
index dd2b6e4affc9..66cdc0e7bf3c 100644
--- a/sound/soc/sof/mediatek/mt8195/Makefile
+++ b/sound/soc/sof/mediatek/mt8195/Makefile
@@ -1,3 +1,3 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
-snd-sof-mt8195-objs := mt8195.o
+snd-sof-mt8195-objs := mt8195.o mt8195-loader.o
obj-$(CONFIG_SND_SOC_SOF_MT8195) += snd-sof-mt8195.o
diff --git a/sound/soc/sof/mediatek/mt8195/mt8195-loader.c b/sound/soc/sof/mediatek/mt8195/mt8195-loader.c
new file mode 100644
index 000000000000..ed18d6379e92
--- /dev/null
+++ b/sound/soc/sof/mediatek/mt8195/mt8195-loader.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
+//
+// Copyright (c) 2021 Mediatek Corporation. All rights reserved.
+//
+// Author: YC Hung <yc.hung@...iatek.com>
+//
+// Hardware interface for mt8195 DSP code loader
+
+#include <sound/sof.h>
+#include "mt8195.h"
+#include "../../ops.h"
+
+void sof_hifixdsp_boot_sequence(struct snd_sof_dev *sdev, u32 boot_addr)
+{
+ /* ADSP bootup base */
+ snd_sof_dsp_write(sdev, DSP_REG_BAR, DSP_ALTRESETVEC, boot_addr);
+
+ /* pull high RunStall (set bit3 to 1) */
+ snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_RESET_SW,
+ ADSP_RUNSTALL, ADSP_RUNSTALL);
+
+ /* pull high StatVectorSel to use AltResetVec (set bit4 to 1) */
+ snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_RESET_SW,
+ DSP_RESET_SW, DSP_RESET_SW);
+
+ /* toggle DReset & BReset */
+ /* pull high DReset & BReset */
+ snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_RESET_SW,
+ ADSP_BRESET_SW | ADSP_DRESET_SW,
+ ADSP_BRESET_SW | ADSP_DRESET_SW);
+
+ /* pull low DReset & BReset */
+ snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_RESET_SW,
+ ADSP_BRESET_SW | ADSP_DRESET_SW,
+ 0);
+
+ /* Enable PDebug */
+ snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_PDEBUGBUS0,
+ PDEBUG_ENABLE,
+ PDEBUG_ENABLE);
+
+ /* release RunStall (set bit3 to 0) */
+ snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_RESET_SW,
+ ADSP_RUNSTALL, 0);
+}
+
+void sof_hifixdsp_shutdown(struct snd_sof_dev *sdev)
+{
+ /* Clear to 0 firstly */
+ snd_sof_dsp_write(sdev, DSP_REG_BAR, DSP_RESET_SW, 0x0);
+
+ /* RUN_STALL pull high again to reset */
+ snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, DSP_RESET_SW,
+ ADSP_RUNSTALL, ADSP_RUNSTALL);
+}
+
diff --git a/sound/soc/sof/mediatek/mt8195/mt8195.c b/sound/soc/sof/mediatek/mt8195/mt8195.c
index 945601a0dc37..88da6c2de070 100644
--- a/sound/soc/sof/mediatek/mt8195/mt8195.c
+++ b/sound/soc/sof/mediatek/mt8195/mt8195.c
@@ -305,6 +305,9 @@ const struct snd_sof_dsp_ops sof_mt8195_ops = {
.probe = mt8195_dsp_probe,
.remove = mt8195_dsp_remove,
+ /* DSP core boot */
+ .run = mt8195_run,
+
/* Block IO */
.block_read = sof_block_read,
.block_write = sof_block_write,
@@ -318,6 +321,11 @@ const struct snd_sof_dsp_ops sof_mt8195_ops = {
/* misc */
.get_bar_index = mt8195_get_bar_index,
+ /* module loading */
+ .load_module = snd_sof_parse_module_memcpy,
+ /* firmware loading */
+ .load_firmware = snd_sof_load_firmware_memcpy,
+
/* Firmware ops */
.dsp_arch_ops = &sof_xtensa_arch_ops,
diff --git a/sound/soc/sof/mediatek/mt8195/mt8195.h b/sound/soc/sof/mediatek/mt8195/mt8195.h
index 48cbbb5aacb5..929424182357 100644
--- a/sound/soc/sof/mediatek/mt8195/mt8195.h
+++ b/sound/soc/sof/mediatek/mt8195/mt8195.h
@@ -10,6 +10,7 @@
#define __MT8195_H
struct mtk_adsp_chip_info;
+struct snd_sof_dev;
#define DSP_REG_BASE 0x10803000
#define SCP_CFGREG_BASE 0x10724000
@@ -152,4 +153,6 @@ struct mtk_adsp_chip_info;
#define DRAM_REMAP_SHIFT 12
#define DRAM_REMAP_MASK (BIT(DRAM_REMAP_SHIFT) - 1)
+void sof_hifixdsp_boot_sequence(struct snd_sof_dev *sdev, u32 boot_addr);
+void sof_hifixdsp_shutdown(struct snd_sof_dev *sdev);
#endif
--
2.27.0
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