lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite for Android: free password hash cracker in your pocket
[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Message-Id: <20211118031841.42315-1-samuel@sholland.org>
Date:   Wed, 17 Nov 2021 21:18:35 -0600
From:   Samuel Holland <samuel@...lland.org>
To:     MyungJoo Ham <myungjoo.ham@...sung.com>,
        Kyungmin Park <kyungmin.park@...sung.com>,
        Chanwoo Choi <cw00.choi@...sung.com>,
        Maxime Ripard <mripard@...nel.org>,
        Chen-Yu Tsai <wens@...e.org>,
        Jernej Skrabec <jernej.skrabec@...il.com>,
        Rob Herring <robh+dt@...nel.org>
Cc:     devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-pm@...r.kernel.org, linux-sunxi@...ts.linux.dev,
        linux-kernel@...r.kernel.org, Samuel Holland <samuel@...lland.org>
Subject: [PATCH v3 0/6] DRAM devfreq support for Allwinner A64/H5

This series adds a new devfreq driver for the MBUS/DRAM controller in
some Allwinner SoCs, and enables it for the A64 and H5.

The binding and DTs are updated in patches 1-5. The MBUS nodes already
existed, but were not bound to any driver before; they were only used
for their dma-ranges property. Finally, the driver is added in patch 6.

I am not quite sure the best way to handle DRAM register range in the
DT binding -- as a separate reg property, a separate node, or simply
enlarging the MBUS register range. While the DRAM controller is a
separate IP block, the MBUS hardware has the ability to double-buffer
certain DRAM controller registers, and the hardware MDFS process writes
to some DRAM controller registers as well. So they are rather tightly
integrated.

Like the driver commit description says, this driver could support
additional SoCs: at least A33, A83T, and H3. I can send follow-up
patches adding compatibles for these, but I cannot test A33 or A83T.

Changes from v2:
  - Remove unnecessary quotes from binding
  - Fix issues with overall minItems/maxItems limits
  - Added tags

Changes from v1:
  - Patch 1 was merged
  - Drop patches 2-4 (support for devfreq drivers without OPPs)
  - Convert the driver to use dynamic OPPs

Samuel Holland (6):
  dt-bindings: clock: sunxi: Export CLK_DRAM for devfreq
  dt-bindings: arm: sunxi: Expand MBUS binding
  dt-bindings: arm: sunxi: Add H5 MBUS compatible
  ARM: dts: sunxi: h3/h5: Update MBUS node
  arm64: dts: allwinner: a64: Update MBUS node
  PM / devfreq: Add a driver for the sun8i/sun50i MBUS

 .../arm/sunxi/allwinner,sun4i-a10-mbus.yaml   |  91 +++-
 arch/arm/boot/dts/sun8i-h3.dtsi               |   4 +
 arch/arm/boot/dts/sunxi-h3-h5.dtsi            |  11 +-
 arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi |  10 +-
 arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi  |   4 +
 drivers/clk/sunxi-ng/ccu-sun50i-a64.h         |   2 -
 drivers/clk/sunxi-ng/ccu-sun8i-h3.h           |   2 -
 drivers/devfreq/Kconfig                       |   8 +
 drivers/devfreq/Makefile                      |   1 +
 drivers/devfreq/sun8i-a33-mbus.c              | 511 ++++++++++++++++++
 include/dt-bindings/clock/sun50i-a64-ccu.h    |   2 +-
 include/dt-bindings/clock/sun8i-h3-ccu.h      |   2 +-
 12 files changed, 634 insertions(+), 14 deletions(-)
 create mode 100644 drivers/devfreq/sun8i-a33-mbus.c

-- 
2.32.0

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ