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Date:   Thu, 18 Nov 2021 10:11:07 +0530
From:   Vinod Koul <vkoul@...nel.org>
To:     Vamsi Krishna Lanka <quic_vamslank@...cinc.com>
Cc:     g@...cinc.com, agross@...nel.org, bjorn.andersson@...aro.org,
        mturquette@...libre.com, sboyd@...nel.org, robh+dt@...nel.org,
        tglx@...utronix.de, maz@...nel.org, linux-arm-msm@...r.kernel.org,
        linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org, manivannan.sadhasivam@...aro.org
Subject: Re: [PATCH v4 2/6] clk: qcom: Add LUCID_EVO PLL type for SDX65

On 17-11-21, 17:54, Vamsi Krishna Lanka wrote:
> On Tue, Nov 16, 2021 at 01:55:29PM +0530, Vinod Koul wrote:
> > On 15-11-21, 23:38, quic_vamslank@...cinc.com wrote:
> > > From: Vamsi Krishna Lanka <quic_vamslank@...cinc.com>

> > > +{
> > > +	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
> > > +	struct regmap *regmap = pll->clkr.regmap;
> > > +	u32 l, frac;
> > > +
> > > +	regmap_read(regmap, PLL_L_VAL(pll), &l);
> > > +	l &= LUCID_EVO_PLL_L_VAL_MASK;
> > > +	regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac);
> > > +
> > > +	return alpha_pll_calc_rate(parent_rate, l, frac, pll_alpha_width(pll));
> > > +}
> > 
> > I think this can use __alpha_pll_trion_set_rate()

> 
> I didn't get with which function are you comparing this. I cannot able to
> find any function similar to this.

This is in upstream, pls see commit: 80ca7765fc75 ("clk: qcom:
clk-alpha-pll: modularize alpha_pll_trion_set_rate()")

-- 
~Vinod

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