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Date: Thu, 18 Nov 2021 09:24:13 +0800
From: kernel test robot <lkp@...el.com>
To: Pali Rohár <pali@...nel.org>
Cc: kbuild-all@...ts.01.org, linux-kernel@...r.kernel.org
Subject: [pali:pci-mvebu 10/63] drivers/pci/pci-bridge-emul.c:216:23:
warning: conversion from 'long unsigned int' to 'unsigned int' changes value
from '18446744073700900863' to '4286316543'
tree: https://git.kernel.org/pub/scm/linux/kernel/git/pali/linux.git pci-mvebu
head: 1da84421034ff2bd51f34e0508485bac6d0f8b48
commit: ac831422ea1706cf7c354ae5d9a1cb1fe4ca45b2 [10/63] PCI: pci-bridge-emul: Fix definitions of reserved bits
config: ia64-randconfig-r011-20211117 (attached as .config)
compiler: ia64-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://git.kernel.org/pub/scm/linux/kernel/git/pali/linux.git/commit/?id=ac831422ea1706cf7c354ae5d9a1cb1fe4ca45b2
git remote add pali https://git.kernel.org/pub/scm/linux/kernel/git/pali/linux.git
git fetch --no-tags pali pci-mvebu
git checkout ac831422ea1706cf7c354ae5d9a1cb1fe4ca45b2
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross ARCH=ia64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@...el.com>
All warnings (new ones prefixed by >>):
>> drivers/pci/pci-bridge-emul.c:216:23: warning: conversion from 'long unsigned int' to 'unsigned int' changes value from '18446744073700900863' to '4286316543' [-Woverflow]
216 | .ro = ~(BIT(23) | PCI_EXP_LNKCAP_CLKPM),
| ^
vim +216 drivers/pci/pci-bridge-emul.c
173
174 static const
175 struct pci_bridge_reg_behavior pcie_cap_regs_behavior[PCI_CAP_PCIE_SIZEOF / 4] = {
176 [PCI_CAP_LIST_ID / 4] = {
177 /*
178 * Capability ID, Next Capability Pointer and
179 * bits [14:0] of Capabilities register are all read-only.
180 * Bit 15 of Capabilities register is reserved.
181 */
182 .ro = GENMASK(30, 0),
183 },
184
185 [PCI_EXP_DEVCAP / 4] = {
186 /*
187 * Bits [31:29] and [17:16] are reserved.
188 * Bits [27:18] are reserved for non-Upstream ports.
189 * Bits 28 and [14:6] are reserved for non-Endpoint devices.
190 * Other bits are read-only.
191 */
192 .ro = BIT(15) | GENMASK(5, 0),
193 },
194
195 [PCI_EXP_DEVCTL / 4] = {
196 /*
197 * Device control register is RW, except bit 15 which is
198 * reserved for non-Endpoints or non-PCIe-to-PCI/X bridges.
199 */
200 .rw = GENMASK(14, 0),
201
202 /*
203 * Device status register has bits 6 and [3:0] W1C, [5:4] RO,
204 * the rest is reserved. Also bit 6 is reserved for non-upstream
205 * ports.
206 */
207 .w1c = GENMASK(3, 0) << 16,
208 .ro = GENMASK(5, 4) << 16,
209 },
210
211 [PCI_EXP_LNKCAP / 4] = {
212 /*
213 * All bits are RO, except bit 23 which is reserved and
214 * bit 18 which is reserved for non-Upstream ports.
215 */
> 216 .ro = ~(BIT(23) | PCI_EXP_LNKCAP_CLKPM),
217 },
218
219 [PCI_EXP_LNKCTL / 4] = {
220 /*
221 * Link control has bits [15:14], [11:3] and [1:0] RW, the
222 * rest is reserved. Bit 8 is reserved for non-upstream ports.
223 *
224 * Link status has bits [13:0] RO, and bits [15:14]
225 * W1C.
226 */
227 .rw = GENMASK(15, 14) | GENMASK(11, 9) | GENMASK(7, 3) | GENMASK(1, 0),
228 .ro = GENMASK(13, 0) << 16,
229 .w1c = GENMASK(15, 14) << 16,
230 },
231
232 [PCI_EXP_SLTCAP / 4] = {
233 .ro = ~0,
234 },
235
236 [PCI_EXP_SLTCTL / 4] = {
237 /*
238 * Slot control has bits [14:0] RW, the rest is
239 * reserved.
240 *
241 * Slot status has bits 8 and [4:0] W1C, bits [7:5] RO, the
242 * rest is reserved.
243 */
244 .rw = GENMASK(14, 0),
245 .w1c = (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
246 PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_PDC |
247 PCI_EXP_SLTSTA_CC | PCI_EXP_SLTSTA_DLLSC) << 16,
248 .ro = (PCI_EXP_SLTSTA_MRLSS | PCI_EXP_SLTSTA_PDS |
249 PCI_EXP_SLTSTA_EIS) << 16,
250 },
251
252 [PCI_EXP_RTCTL / 4] = {
253 /*
254 * Root control has bits [4:0] RW, the rest is
255 * reserved.
256 *
257 * Root capabilities has bit 0 RO, the rest is reserved.
258 */
259 .rw = (PCI_EXP_RTCTL_SECEE | PCI_EXP_RTCTL_SENFEE |
260 PCI_EXP_RTCTL_SEFEE | PCI_EXP_RTCTL_PMEIE |
261 PCI_EXP_RTCTL_CRSSVE),
262 .ro = PCI_EXP_RTCAP_CRSVIS << 16,
263 },
264
265 [PCI_EXP_RTSTA / 4] = {
266 /*
267 * Root status has bits 17 and [15:0] RO, bit 16 W1C, the rest
268 * is reserved.
269 */
270 .ro = GENMASK(15, 0) | PCI_EXP_RTSTA_PENDING,
271 .w1c = PCI_EXP_RTSTA_PME,
272 },
273
274 [PCI_EXP_DEVCAP2 / 4] = {
275 /*
276 * Device capabilities 2 register has reserved bits [30:27].
277 * Also bits [26:24] are reserved for non-upstream ports.
278 */
279 .ro = BIT(31) | GENMASK(23, 0),
280 },
281
282 [PCI_EXP_DEVCTL2 / 4] = {
283 /*
284 * Device control 2 register is RW. Bit 11 is reserved for
285 * non-upstream ports.
286 *
287 * Device status 2 register is reserved.
288 */
289 .rw = GENMASK(15, 12) | GENMASK(10, 0),
290 },
291
292 [PCI_EXP_LNKCAP2 / 4] = {
293 /* Link capabilities 2 register has reserved bits [30:25] and 0. */
294 .ro = BIT(31) | GENMASK(24, 1),
295 },
296
297 [PCI_EXP_LNKCTL2 / 4] = {
298 /*
299 * Link control 2 register is RW.
300 *
301 * Link status 2 register has bits 5, 15 W1C;
302 * bits 10, 11 reserved and others are RO.
303 */
304 .rw = GENMASK(15, 0),
305 .w1c = (BIT(15) | BIT(5)) << 16,
306 .ro = (GENMASK(14, 12) | GENMASK(9, 6) | GENMASK(4, 0)) << 16,
307 },
308
309 [PCI_EXP_SLTCAP2 / 4] = {
310 /* Slot capabilities 2 register is reserved. */
311 },
312
313 [PCI_EXP_SLTCTL2 / 4] = {
314 /* Both Slot control 2 and Slot status 2 registers are reserved. */
315 },
316 };
317
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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