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Message-ID: <d029d5e6-5b32-972d-943e-64264e599c3d@redhat.com>
Date: Thu, 18 Nov 2021 14:23:56 +0100
From: Paolo Bonzini <pbonzini@...hat.com>
To: Like Xu <like.xu.linux@...il.com>
Cc: Joerg Roedel <joro@...tes.org>,
Kim Phillips <kim.phillips@....com>,
Jim Mattson <jmattson@...gle.com>,
Maxim Levitsky <mlevitsk@...hat.com>,
Sean Christopherson <seanjc@...gle.com>,
Vitaly Kuznetsov <vkuznets@...hat.com>,
Wanpeng Li <wanpengli@...cent.com>, kvm@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH] KVM: x86/pmu: Fix reserved bits for AMD PerfEvtSeln
register
On 11/18/21 14:03, Like Xu wrote:
>
> This is because according to APM (Revision: 4.03) Figure 13-7,
> the bits [35:32] of AMD PerfEvtSeln register is a part of the
> event select encoding, which extends the EVENT_SELECT field
> from 8 bits to 12 bits.
Queued, thanks.
Paolo
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