[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <20211119183833.1402635-1-miquel.raynal@bootlin.com>
Date: Fri, 19 Nov 2021 19:38:33 +0100
From: Miquel Raynal <miquel.raynal@...tlin.com>
To: Herve Codina <herve.codina@...tlin.com>,
Miquel Raynal <miquel.raynal@...tlin.com>,
Richard Weinberger <richard@....at>,
Vignesh Raghavendra <vigneshr@...com>
Cc: linux-mtd@...ts.infradead.org, linux-kernel@...r.kernel.org,
Thomas Petazzoni <thomas.petazzoni@...tlin.com>
Subject: Re: [PATCH v3 4/4] mtd: rawnand: fsmc: Fix timing computation
On Fri, 2021-11-19 at 15:03:16 UTC, Herve Codina wrote:
> Under certain circumstances, the timing settings calculated by
> the FSMC NAND controller driver were inaccurate.
> These settings led to incorrect data reads or fallback to
> timing mode 0 depending on the NAND chip used.
>
> The timing computation did not take into account the following
> constraint given in SPEAr3xx reference manual:
> twait >= tCEA - (tset * TCLK) + TOUTDEL + TINDEL
>
> Enhance the timings calculation by taking into account this
> additional constraint.
>
> This change has no impact on slow timing modes such as mode 0.
> Indeed, on mode 0, computed values are the same with and
> without the patch.
>
> NANDs which previously stayed in mode 0 because of fallback to
> mode 0 can now work at higher speeds and NANDs which were not
> working at all because of the corrupted data work at high
> speeds without troubles.
>
> Overall improvement on a Micron/MT29F1G08 (flash_speed tool):
> mode0 mode3
> eraseblock write speed 3220 KiB/s 4511 KiB/s
> eraseblock read speed 4491 KiB/s 7529 KiB/s
>
> Fixes: d9fb079571833 ("mtd: nand: fsmc: add support for SDR timings")
> Signed-off-by: Herve Codina <herve.codina@...tlin.com>
Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git mtd/fixes, thanks.
Miquel
Powered by blists - more mailing lists