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Date: Sun, 21 Nov 2021 12:44:29 +0800
From: kernel test robot <lkp@...el.com>
To: Vladimir Stempen <vladimir.stempen@....com>
Cc: kbuild-all@...ts.01.org, linux-kernel@...r.kernel.org,
Alex Deucher <alexander.deucher@....com>
Subject: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_optc.c:312:6:
warning: no previous prototype for 'optc2_align_vblanks'
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head: 923dcc5eb0c111eccd51cc7ce1658537e3c38b25
commit: 77a2b7265f20ee827e527eaa6f82b87e88388947 drm/amd/display: Synchronize displays with different timings
date: 9 months ago
config: x86_64-randconfig-m001-20211109 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce (this is a W=1 build):
# https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=77a2b7265f20ee827e527eaa6f82b87e88388947
git remote add linus https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
git fetch --no-tags linus master
git checkout 77a2b7265f20ee827e527eaa6f82b87e88388947
# save the attached .config to linux build tree
make W=1 ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@...el.com>
All warnings (new ones prefixed by >>):
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_optc.c:80:6: warning: no previous prototype for 'optc2_set_timing_db_mode' [-Wmissing-prototypes]
80 | void optc2_set_timing_db_mode(struct timing_generator *optc, bool enable)
| ^~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_optc.c:114:6: warning: no previous prototype for 'optc2_use_gsl_as_master_update_lock' [-Wmissing-prototypes]
114 | void optc2_use_gsl_as_master_update_lock(struct timing_generator *optc,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_optc.c:124:6: warning: no previous prototype for 'optc2_set_gsl_window' [-Wmissing-prototypes]
124 | void optc2_set_gsl_window(struct timing_generator *optc,
| ^~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_optc.c:142:6: warning: no previous prototype for 'optc2_set_vupdate_keepout' [-Wmissing-prototypes]
142 | void optc2_set_vupdate_keepout(struct timing_generator *optc,
| ^~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_optc.c:176:6: warning: no previous prototype for 'optc2_set_dsc_encoder_frame_start' [-Wmissing-prototypes]
176 | void optc2_set_dsc_encoder_frame_start(struct timing_generator *optc,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_optc.c:299:6: warning: no previous prototype for 'optc2_set_dwb_source' [-Wmissing-prototypes]
299 | void optc2_set_dwb_source(struct timing_generator *optc,
| ^~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_optc.c:312:6: warning: no previous prototype for 'optc2_align_vblanks' [-Wmissing-prototypes]
312 | void optc2_align_vblanks(
| ^~~~~~~~~~~~~~~~~~~
--
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:74:6: warning: no previous prototype for 'print_microsec' [-Wmissing-prototypes]
74 | void print_microsec(struct dc_context *dc_ctx,
| ^~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:129:6: warning: no previous prototype for 'dcn10_log_hubbub_state' [-Wmissing-prototypes]
129 | void dcn10_log_hubbub_state(struct dc *dc, struct dc_log_buffer_ctx *log_ctx)
| ^~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:1854:10: warning: no previous prototype for 'reduceSizeAndFraction' [-Wmissing-prototypes]
1854 | uint64_t reduceSizeAndFraction(
| ^~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:1900:6: warning: no previous prototype for 'is_low_refresh_rate' [-Wmissing-prototypes]
1900 | bool is_low_refresh_rate(struct pipe_ctx *pipe)
| ^~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:1909:9: warning: no previous prototype for 'get_clock_divider' [-Wmissing-prototypes]
1909 | uint8_t get_clock_divider(struct pipe_ctx *pipe, bool account_low_refresh_rate)
| ^~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:1929:5: warning: no previous prototype for 'dcn10_align_pixel_clocks' [-Wmissing-prototypes]
1929 | int dcn10_align_pixel_clocks(
| ^~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c: In function 'dcn10_align_pixel_clocks':
>> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:1944:7: warning: variable 'clamshell_closed' set but not used [-Wunused-but-set-variable]
1944 | bool clamshell_closed = false;
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c: At top level:
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hw_sequencer.c:2344:6: warning: no previous prototype for 'dcn10_program_pte_vm' [-Wmissing-prototypes]
2344 | void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp)
| ^~~~~~~~~~~~~~~~~~~~
vim +/optc2_align_vblanks +312 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_optc.c
311
> 312 void optc2_align_vblanks(
313 struct timing_generator *optc_master,
314 struct timing_generator *optc_slave,
315 uint32_t master_pixel_clock_100Hz,
316 uint32_t slave_pixel_clock_100Hz,
317 uint8_t master_clock_divider,
318 uint8_t slave_clock_divider)
319 {
320 /* accessing slave OTG registers */
321 struct optc *optc1 = DCN10TG_FROM_TG(optc_slave);
322
323 uint32_t master_v_active = 0;
324 uint32_t master_h_total = 0;
325 uint32_t slave_h_total = 0;
326 uint64_t L, XY, p = 10000;
327 uint32_t X, Y;
328 uint32_t master_update_lock;
329
330 /* disable slave OTG */
331 REG_UPDATE(OTG_CONTROL, OTG_MASTER_EN, 0);
332 /* wait until disabled */
333 REG_WAIT(OTG_CONTROL,
334 OTG_CURRENT_MASTER_EN_STATE,
335 0, 10, 5000);
336
337 REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &slave_h_total);
338
339 /* assign slave OTG to be controlled by master update lock */
340 REG_SET(OTG_GLOBAL_CONTROL0, 0,
341 OTG_MASTER_UPDATE_LOCK_SEL, optc_master->inst);
342
343 /* accessing master OTG registers */
344 optc1 = DCN10TG_FROM_TG(optc_master);
345
346 /* saving update lock state, not sure if it's needed */
347 REG_GET(OTG_MASTER_UPDATE_LOCK,
348 OTG_MASTER_UPDATE_LOCK, &master_update_lock);
349 /* unlocking master OTG */
350 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
351 OTG_MASTER_UPDATE_LOCK, 0);
352
353 REG_GET(OTG_V_BLANK_START_END,
354 OTG_V_BLANK_START, &master_v_active);
355 REG_GET(OTG_H_TOTAL, OTG_H_TOTAL, &master_h_total);
356
357 /* calculate when to enable slave OTG */
358 L = p * slave_h_total * master_pixel_clock_100Hz /
359 master_h_total / slave_pixel_clock_100Hz;
360 XY = L / p;
361 Y = master_v_active - XY - 1;
362 X = ((XY + 1) * p - L) * master_h_total / master_clock_divider / p;
363
364 /*
365 * set master OTG to unlock when V/H
366 * counters reach calculated values
367 */
368 REG_UPDATE(OTG_GLOBAL_CONTROL1,
369 MASTER_UPDATE_LOCK_DB_EN, 1);
370 REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
371 MASTER_UPDATE_LOCK_DB_X,
372 X,
373 MASTER_UPDATE_LOCK_DB_Y,
374 Y);
375
376 /* lock master OTG */
377 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
378 OTG_MASTER_UPDATE_LOCK, 1);
379 REG_WAIT(OTG_MASTER_UPDATE_LOCK,
380 UPDATE_LOCK_STATUS, 1, 1, 10);
381
382 /* accessing slave OTG registers */
383 optc1 = DCN10TG_FROM_TG(optc_slave);
384
385 /*
386 * enable slave OTG, the OTG is locked with
387 * master's update lock, so it will not run
388 */
389 REG_UPDATE(OTG_CONTROL,
390 OTG_MASTER_EN, 1);
391
392 /* accessing master OTG registers */
393 optc1 = DCN10TG_FROM_TG(optc_master);
394
395 /*
396 * unlock master OTG. When master H/V counters reach
397 * DB_XY point, slave OTG will start
398 */
399 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
400 OTG_MASTER_UPDATE_LOCK, 0);
401
402 /* accessing slave OTG registers */
403 optc1 = DCN10TG_FROM_TG(optc_slave);
404
405 /* wait for slave OTG to start running*/
406 REG_WAIT(OTG_CONTROL,
407 OTG_CURRENT_MASTER_EN_STATE,
408 1, 10, 5000);
409
410 /* accessing master OTG registers */
411 optc1 = DCN10TG_FROM_TG(optc_master);
412
413 /* disable the XY point*/
414 REG_UPDATE(OTG_GLOBAL_CONTROL1,
415 MASTER_UPDATE_LOCK_DB_EN, 0);
416 REG_UPDATE_2(OTG_GLOBAL_CONTROL1,
417 MASTER_UPDATE_LOCK_DB_X,
418 0,
419 MASTER_UPDATE_LOCK_DB_Y,
420 0);
421
422 /*restore master update lock*/
423 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
424 OTG_MASTER_UPDATE_LOCK, master_update_lock);
425
426 /* accessing slave OTG registers */
427 optc1 = DCN10TG_FROM_TG(optc_slave);
428 /* restore slave to be controlled by it's own */
429 REG_SET(OTG_GLOBAL_CONTROL0, 0,
430 OTG_MASTER_UPDATE_LOCK_SEL, optc_slave->inst);
431
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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