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Message-ID: <a28532b1-bfa0-031b-91cc-070cad557599@canonical.com>
Date: Tue, 23 Nov 2021 20:47:57 +0100
From: Krzysztof Kozlowski <krzysztof.kozlowski@...onical.com>
To: Roger Quadros <rogerq@...nel.org>, tony@...mide.com
Cc: kishon@...com, nm@...com, vigneshr@...com,
linux-omap@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, Rob Herring <robh+dt@...nel.org>
Subject: Re: [PATCH 1/4] dt-bindings: memory-controllers: ti,gpmc: Add
compatible for AM64
On 23/11/2021 11:26, Roger Quadros wrote:
> AM64 SoC contains the GPMC module. Add compatible for it.
>
> Newer SoCs don't necessarily map GPMC data region at the same place
> as legacy SoCs. Add reg-names "data", to provide this information to
> the device driver.
>
> Cc: Rob Herring <robh+dt@...nel.org>
> Signed-off-by: Roger Quadros <rogerq@...nel.org>
> ---
> .../bindings/memory-controllers/ti,gpmc.yaml | 12 +++++++++++-
> 1 file changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/memory-controllers/ti,gpmc.yaml b/Documentation/devicetree/bindings/memory-controllers/ti,gpmc.yaml
> index 25b42d68f9b3..1869cc6f949b 100644
> --- a/Documentation/devicetree/bindings/memory-controllers/ti,gpmc.yaml
> +++ b/Documentation/devicetree/bindings/memory-controllers/ti,gpmc.yaml
> @@ -23,13 +23,20 @@ properties:
> items:
> - enum:
> - ti,am3352-gpmc
> + - ti,am64-gpmc
> - ti,omap2420-gpmc
> - ti,omap2430-gpmc
> - ti,omap3430-gpmc
> - ti,omap4430-gpmc
>
> reg:
> - maxItems: 1
> + minItems: 1
> + maxItems: 2
> +
> + reg-names:
> + items:
> + - const: cfg
> + - const: data
I see your driver handles cases with only one reg item, but I have other
question - is it correct to have older (ARMv7) platform with two reg
items? Or can am64-gpmc come with only one reg?
IOW, I am surprised there is no if-else case precising this minItems
requirement for different SocS.
>
> interrupts:
> maxItems: 1
> @@ -44,6 +51,9 @@ properties:
> items:
> - const: fck
>
> + power-domains:
> + maxItems: 1
Similar, but looks like a weaker requirement - could an older SoC define
power-domain?
> +
> dmas:
> items:
> - description: DMA channel for GPMC NAND prefetch
>
Best regards,
Krzysztof
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