linux-kernel - Re: [PATCH 01/13] dt-bindings: interrupt-controller: create a header for RISC-V interrupts

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <272946671.hFph3VMliC@diego>
Date:   Tue, 23 Nov 2021 12:07:52 +0100
From:   Heiko Stübner <heiko@...ech.de>
To:     linus.walleij@...aro.org, bgolaszewski@...libre.com,
        robh+dt@...nel.org, jassisinghbrar@...il.com,
        paul.walmsley@...ive.com, palmer@...belt.com,
        aou@...s.berkeley.edu, a.zummo@...ertech.it,
        alexandre.belloni@...tlin.com, broonie@...nel.org,
        gregkh@...uxfoundation.org, lewis.hanly@...rochip.com,
        conor.dooley@...rochip.com, daire.mcnamara@...rochip.com,
        atish.patra@....com, ivan.griffin@...rochip.com,
        linux-gpio@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-i2c@...r.kernel.org,
        linux-riscv@...ts.infradead.org, linux-crypto@...r.kernel.org,
        linux-rtc@...r.kernel.org, linux-spi@...r.kernel.org,
        linux-usb@...r.kernel.org
Cc:     krzysztof.kozlowski@...onical.com, geert@...ux-m68k.org,
        bin.meng@...driver.com, conor.dooley@...rochip.com
Subject: Re: [PATCH 01/13] dt-bindings: interrupt-controller: create a header for RISC-V interrupts

Am Montag, 8. November 2021, 16:05:42 CET schrieb conor.dooley@...rochip.com:
> From: Ivan Griffin <ivan.griffin@...rochip.com>
> 
> Provide named identifiers for device tree for RISC-V interrupts.
> 
> Licensed under GPL and MIT, as this file may be useful to any OS that
> uses device tree.
> 
> Signed-off-by: Ivan Griffin <ivan.griffin@...rochip.com>
> Signed-off-by: Conor Dooley <conor.dooley@...rochip.com>
> ---
>  .../interrupt-controller/riscv-hart.h         | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
>  create mode 100644 include/dt-bindings/interrupt-controller/riscv-hart.h
> 
> diff --git a/include/dt-bindings/interrupt-controller/riscv-hart.h b/include/dt-bindings/interrupt-controller/riscv-hart.h
> new file mode 100644
> index 000000000000..e1c32f6090ac
> --- /dev/null
> +++ b/include/dt-bindings/interrupt-controller/riscv-hart.h
> @@ -0,0 +1,19 @@
> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
> +/*
> + * Copyright (C) 2021 Microchip Technology Inc.  All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H
> +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H
> +
> +#define HART_INT_U_SOFT   0
> +#define HART_INT_S_SOFT   1
> +#define HART_INT_M_SOFT   3
> +#define HART_INT_U_TIMER  4
> +#define HART_INT_S_TIMER  5
> +#define HART_INT_M_TIMER  7
> +#define HART_INT_U_EXT    8
> +#define HART_INT_S_EXT    9
> +#define HART_INT_M_EXT    11

(1) From checking clic doc [0] I see an additional
	12   CLIC software interrupt
defined.

(2) The doc states that the ordering is a recommendation and
	"not mandatory in all incarnations of the CLIC"
Is that clarified somewhere else that this more than recommended?

Thanks
Heiko


[0] https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc

> +
> +#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H */
>