linux-kernel - Re: [PATCH v2] clk: qcom: clk-alpha-pll: Don't reconfigure running Trion

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Message-ID: <CAG3jFyv4uhEN9zO0Kt9QU+0i93YoT7ccpSN-amncQM=zM9r6JQ@mail.gmail.com>
Date:   Tue, 23 Nov 2021 18:02:44 +0100
From:   Robert Foss <robert.foss@...aro.org>
To:     Bjorn Andersson <bjorn.andersson@...aro.org>
Cc:     Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Taniya Das <tdas@...eaurora.org>,
        Vinod Koul <vkoul@...nel.org>, linux-arm-msm@...r.kernel.org,
        linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2] clk: qcom: clk-alpha-pll: Don't reconfigure running Trion

Hey Bjorn,

On Tue, 23 Nov 2021 at 17:23, Bjorn Andersson
<bjorn.andersson@...aro.org> wrote:
>
> In the event that the bootloader has configured the Trion PLL as source
> for the display clocks, e.g. for the continuous splashscreen, then there
> will also be RCGs that are clocked by this instance.
>
> Reconfiguring, and in particular disabling the output of, the PLL will
> cause issues for these downstream RCGs and has been shown to prevent
> them from being re-parented.
>
> Follow downstream and skip configuration if it's determined that the PLL
> is already running.
>
> Fixes: 59128c20a6a9 ("clk: qcom: clk-alpha-pll: Add support for controlling Lucid PLLs")
> Signed-off-by: Bjorn Andersson <bjorn.andersson@...aro.org>
> ---
>
> Changes since v1:
> - Forgot to commit the last minute s/pr_dbg/pr_debug/
>
>  drivers/clk/qcom/clk-alpha-pll.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
>
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
> index eaedcceb766f..8f65b9bdafce 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -1429,6 +1429,15 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);
>  void clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
>                              const struct alpha_pll_config *config)
>  {
> +       /*
> +        * If the bootloader left the PLL enabled it's likely that there are
> +        * RCGs that will lock up if we disable the PLL below.
> +        */
> +       if (trion_pll_is_enabled(pll, regmap)) {
> +               pr_debug("Trion PLL is already enabled, skipping configuration\n");
> +               return;
> +       }
> +
>         clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
>         regmap_write(regmap, PLL_CAL_L_VAL(pll), TRION_PLL_CAL_VAL);
>         clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
> --
> 2.33.1

This resolves an issue I was seeing related to clocks not being able
to get updated.

Reviewed-by: Robert Foss <robert.foss@...aro.org>