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Message-Id: <20211124115726.991024576@linuxfoundation.org>
Date: Wed, 24 Nov 2021 12:58:46 +0100
From: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
To: linux-kernel@...r.kernel.org
Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
stable@...r.kernel.org, XiangBing Foo <XiangBing.Foo@....com>,
Martin Leung <Martin.Leung@....com>,
Qingqing Zhuo <qingqing.zhuo@....com>,
Alvin Lee <Alvin.Lee2@....com>,
Daniel Wheeler <Daniel.Wheeler@....com>,
Alex Deucher <alexander.deucher@....com>
Subject: [PATCH 5.15 239/279] drm/amd/display: Update swizzle mode enums
From: Alvin Lee <Alvin.Lee2@....com>
commit 58065a1e524de30df9a2d8214661d5d7eed0a2d9 upstream.
[Why]
Swizzle mode enum for DC_SW_VAR_R_X was existing,
but not mapped correctly.
[How]
Update mapping and conversion for DC_SW_VAR_R_X.
Reviewed-by: XiangBing Foo <XiangBing.Foo@....com>
Reviewed-by: Martin Leung <Martin.Leung@....com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@....com>
Signed-off-by: Alvin Lee <Alvin.Lee2@....com>
Cc: stable@...r.kernel.org
Tested-by: Daniel Wheeler <Daniel.Wheeler@....com>
Signed-off-by: Alex Deucher <alexander.deucher@....com>
Signed-off-by: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
---
drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 4 +++-
drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h | 4 ++--
2 files changed, 5 insertions(+), 3 deletions(-)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1854,7 +1854,9 @@ static void swizzle_to_dml_params(
case DC_SW_VAR_D_X:
*sw_mode = dm_sw_var_d_x;
break;
-
+ case DC_SW_VAR_R_X:
+ *sw_mode = dm_sw_var_r_x;
+ break;
default:
ASSERT(0); /* Not supported */
break;
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
@@ -80,11 +80,11 @@ enum dm_swizzle_mode {
dm_sw_SPARE_13 = 24,
dm_sw_64kb_s_x = 25,
dm_sw_64kb_d_x = 26,
- dm_sw_SPARE_14 = 27,
+ dm_sw_64kb_r_x = 27,
dm_sw_SPARE_15 = 28,
dm_sw_var_s_x = 29,
dm_sw_var_d_x = 30,
- dm_sw_64kb_r_x,
+ dm_sw_var_r_x = 31,
dm_sw_gfx7_2d_thin_l_vp,
dm_sw_gfx7_2d_thin_gl,
};
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