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Message-ID: <87v90hjg7r.ffs@tglx>
Date: Thu, 25 Nov 2021 00:18:00 +0100
From: Thomas Gleixner <tglx@...utronix.de>
To: Arnd Bergmann <arnd@...db.de>,
André Almeida <andrealmeid@...labora.com>
Cc: Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
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"open list:TENSILICA XTENSA PORT (xtensa)"
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Will Deacon <will@...nel.org>
Subject: Re: [PATCH 1/1] futex: Wireup futex_waitv syscall
On Wed, Nov 24 2021 at 15:29, Arnd Bergmann wrote:
> On Wed, Nov 24, 2021 at 2:21 PM André Almeida <andrealmeid@...labora.com> wrote:
>>
>> Wireup futex_waitv syscall for all remaining archs.
>>
>> Signed-off-by: André Almeida <andrealmeid@...labora.com>
>
> Reviewed-by: Arnd Bergmann <arnd@...db.de>
>
> I double-checked that futex_waitv() doesn't need any architecture specific
> hacks, and that the list above is complete.
>
> Should I take this through the asm-generic tree, or would you send it
> through the tip tree?
Feel free to pick it up.
Thanks,
tglx
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