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Message-Id: <890780d3db0c2458b7ffa83636cbf214162e1e3d.1637799475.git.isaku.yamahata@intel.com>
Date: Wed, 24 Nov 2021 16:19:45 -0800
From: isaku.yamahata@...el.com
To: Thomas Gleixner <tglx@...utronix.de>,
Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
"H . Peter Anvin" <hpa@...or.com>,
Paolo Bonzini <pbonzini@...hat.com>,
Vitaly Kuznetsov <vkuznets@...hat.com>,
Wanpeng Li <wanpengli@...cent.com>,
Jim Mattson <jmattson@...gle.com>,
Joerg Roedel <joro@...tes.org>, erdemaktas@...gle.com,
Connor Kuehl <ckuehl@...hat.com>,
Sean Christopherson <seanjc@...gle.com>,
linux-kernel@...r.kernel.org, kvm@...r.kernel.org
Cc: isaku.yamahata@...el.com, isaku.yamahata@...il.com,
Xiaoyao Li <xiaoyao.li@...el.com>
Subject: [RFC PATCH v3 02/59] x86/mtrr: mask out keyid bits from variable mtrr mask register
From: Isaku Yamahata <isaku.yamahata@...el.com>
This is a preparation for TDX support. TDX repurposes high bits of physcial
address to private key ID similarly to MKTME.
IA32_TME_ACTIVATE.MK_TME_KEYID_BITS has same meaning for both TDX
disabled/enable for compatibility.
MTRR calculates mask based on available physical address bits. MKTME
repurpose high bit of physical address to key id for key id. CPUID MAX_PA
remains same and the bits stolen for key id is controlled IA32_TME_ACTIVATE
MSR bit 35:32. Because Key ID bits shouldn't affects memory cachability,
MTRR mask should exclude bits repourposed for Key ID. It's OS
responsibility to maintain cache coherency. detect_tme @
arch/x86/kernel/cpu/intel.c detects tme and destract it from total usable
physical bits. This patch adds same logic needed for MTRR.
Co-developed-by: Xiaoyao Li <xiaoyao.li@...el.com>
Signed-off-by: Xiaoyao Li <xiaoyao.li@...el.com>
Signed-off-by: Isaku Yamahata <isaku.yamahata@...el.com>
---
arch/x86/kernel/cpu/mtrr/mtrr.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtrr.c
index 2746cac9d8a9..79eaf6ed20a6 100644
--- a/arch/x86/kernel/cpu/mtrr/mtrr.c
+++ b/arch/x86/kernel/cpu/mtrr/mtrr.c
@@ -713,6 +713,15 @@ void __init mtrr_bp_init(void)
boot_cpu_data.x86_stepping == 0x4))
phys_addr = 36;
+ if (boot_cpu_has(X86_FEATURE_TME)) {
+ u64 tme_activate;
+
+ rdmsrl(MSR_IA32_TME_ACTIVATE, tme_activate);
+ if (TME_ACTIVATE_LOCKED(tme_activate) &&
+ TME_ACTIVATE_ENABLED(tme_activate)) {
+ phys_addr -= TME_ACTIVATE_KEYID_BITS(tme_activate);
+ }
+ }
size_or_mask = SIZE_OR_MASK_BITS(phys_addr);
size_and_mask = ~size_or_mask & 0xfffff00000ULL;
} else if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR &&
--
2.25.1
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