[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <163785982037.11128.2338335240854330231.tip-bot2@tip-bot2>
Date: Thu, 25 Nov 2021 17:03:40 -0000
From: "irqchip-bot for Billy Tsai" <tip-bot2@...utronix.de>
To: linux-kernel@...r.kernel.org
Cc: Billy Tsai <billy_tsai@...eedtech.com>,
Joel Stanley <joel@....id.au>, Marc Zyngier <maz@...nel.org>,
stable@...r.kernel.org, tglx@...utronix.de
Subject: [irqchip: irq/irqchip-fixes] irqchip/aspeed-scu: Replace update_bits
with write_bits.
The following commit has been merged into the irq/irqchip-fixes branch of irqchip:
Commit-ID: 8958389681b929fcc7301e7dc5f0da12e4a256a0
Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/8958389681b929fcc7301e7dc5f0da12e4a256a0
Author: Billy Tsai <billy_tsai@...eedtech.com>
AuthorDate: Wed, 24 Nov 2021 17:43:48 +08:00
Committer: Marc Zyngier <maz@...nel.org>
CommitterDate: Thu, 25 Nov 2021 16:50:44
irqchip/aspeed-scu: Replace update_bits with write_bits.
The interrupt status bits are cleared by writing 1, we should force a
write to clear the interrupt without checking if the value has changed.
Fixes: 04f605906ff0 ("irqchip: Add Aspeed SCU interrupt controller")
Signed-off-by: Billy Tsai <billy_tsai@...eedtech.com>
Reviewed-by: Joel Stanley <joel@....id.au>
Signed-off-by: Marc Zyngier <maz@...nel.org>
Link: https://lore.kernel.org/r/20211124094348.11621-1-billy_tsai@aspeedtech.com
Cc: stable@...r.kernel.org
---
drivers/irqchip/irq-aspeed-scu-ic.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-aspeed-scu-ic.c b/drivers/irqchip/irq-aspeed-scu-ic.c
index f3c6855..18b77c3 100644
--- a/drivers/irqchip/irq-aspeed-scu-ic.c
+++ b/drivers/irqchip/irq-aspeed-scu-ic.c
@@ -76,8 +76,8 @@ static void aspeed_scu_ic_irq_handler(struct irq_desc *desc)
generic_handle_domain_irq(scu_ic->irq_domain,
bit - scu_ic->irq_shift);
- regmap_update_bits(scu_ic->scu, scu_ic->reg, mask,
- BIT(bit + ASPEED_SCU_IC_STATUS_SHIFT));
+ regmap_write_bits(scu_ic->scu, scu_ic->reg, mask,
+ BIT(bit + ASPEED_SCU_IC_STATUS_SHIFT));
}
chained_irq_exit(chip, desc);
Powered by blists - more mailing lists