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Message-ID: <YaEiRt+vqt1Ix8xb@lunn.ch>
Date:   Fri, 26 Nov 2021 19:07:02 +0100
From:   Andrew Lunn <andrew@...n.ch>
To:     Wells Lu 呂芳騰 <wells.lu@...plus.com>
Cc:     Wells Lu <wellslutw@...il.com>,
        "davem@...emloft.net" <davem@...emloft.net>,
        "kuba@...nel.org" <kuba@...nel.org>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "p.zabel@...gutronix.de" <p.zabel@...gutronix.de>,
        Vincent Shih 施錕鴻 
        <vincent.shih@...plus.com>
Subject: Re: [PATCH v2 2/2] net: ethernet: Add driver for Sunplus SP7021

On Fri, Nov 26, 2021 at 04:12:46PM +0000, Wells Lu 呂芳騰 wrote:
> Hi Andrew,
> 
> 
> From data provided by ASIC engineer, MAC of SP7021 only
> reads the 4 registers of PHY:
> 0: Control register
> 1: Status register

This is the register which has latching of the link
status. genphy_update_link() expects this latching behaviour, and if
the hardware reads the register, that behaviour is not going to
happen.

	Andrew

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