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Message-Id: <20211126181500.3404129-2-daniel.lezcano@linaro.org>
Date:   Fri, 26 Nov 2021 19:14:55 +0100
From:   Daniel Lezcano <daniel.lezcano@...aro.org>
To:     daniel.lezcano@...aro.org
Cc:     robh@...nel.org, arnd@...aro.org, heiko@...ech.de,
        ulf.hansson@...aro.org, rjw@...ysocki.net,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-pm@...r.kernel.org, lukasz.luba@....com,
        Robin Murphy <robin.murphy@....com>,
        Rob Herring <robh+dt@...nel.org>,
        Johan Jonker <jbx6244@...il.com>,
        Helen Koike <helen.koike@...labora.com>,
        Brian Norris <briannorris@...omium.org>,
        Shunqian Zheng <zhengsq@...k-chips.com>,
        Elaine Zhang <zhangqing@...k-chips.com>,
        linux-arm-kernel@...ts.infradead.org (moderated list:ARM/Rockchip SoC
        support),
        linux-rockchip@...ts.infradead.org (open list:ARM/Rockchip SoC support)
Subject: [PATCH v2 2/5] arm64: dts: rockchip: Add powerzones definition for rock960

Add the powerzones description. This first step introduces the big,
the little and the gpu as a powerzone place.

Cc: Robin Murphy <robin.murphy@....com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@...aro.org>
---
   V1: Initial post
   V2:
     - Move description in the SoC dtsi specific file
---
 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 25 ++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index d3cdf6f42a30..3c0dbc0cb2bc 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -76,6 +76,8 @@ cpu_l0: cpu@0 {
 			#cooling-cells = <2>; /* min followed by max */
 			dynamic-power-coefficient = <100>;
 			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+			#powerzone-cells = <0>;
+			powerzone = <&PKG_PZ>;
 		};
 
 		cpu_l1: cpu@1 {
@@ -88,6 +90,8 @@ cpu_l1: cpu@1 {
 			#cooling-cells = <2>; /* min followed by max */
 			dynamic-power-coefficient = <100>;
 			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+			#powerzone-cells = <0>;
+			powerzone = <&PKG_PZ>;
 		};
 
 		cpu_l2: cpu@2 {
@@ -100,6 +104,8 @@ cpu_l2: cpu@2 {
 			#cooling-cells = <2>; /* min followed by max */
 			dynamic-power-coefficient = <100>;
 			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+			#powerzone-cells = <0>;
+			powerzone = <&PKG_PZ>;
 		};
 
 		cpu_l3: cpu@3 {
@@ -112,6 +118,8 @@ cpu_l3: cpu@3 {
 			#cooling-cells = <2>; /* min followed by max */
 			dynamic-power-coefficient = <100>;
 			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+			#powerzone-cells = <0>;
+			powerzone = <&PKG_PZ>;
 		};
 
 		cpu_b0: cpu@100 {
@@ -124,6 +132,8 @@ cpu_b0: cpu@100 {
 			#cooling-cells = <2>; /* min followed by max */
 			dynamic-power-coefficient = <436>;
 			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+			#powerzone-cells = <0>;
+			powerzone = <&PKG_PZ>;
 
 			thermal-idle {
 				#cooling-cells = <2>;
@@ -142,6 +152,8 @@ cpu_b1: cpu@101 {
 			#cooling-cells = <2>; /* min followed by max */
 			dynamic-power-coefficient = <436>;
 			cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
+			#powerzone-cells = <0>;
+			powerzone = <&PKG_PZ>;
 
 			thermal-idle {
 				#cooling-cells = <2>;
@@ -791,6 +803,17 @@ spi5: spi@...00000 {
 		status = "disabled";
 	};
 
+	powerzones {
+
+		PKG_PZ: pkg {
+			#powerzone-cells = <0>;
+                        powerzone = <&SOC_PZ>;
+		};
+
+		SOC_PZ: soc {
+		};
+	};
+
 	thermal_zones: thermal-zones {
 		cpu_thermal: cpu-thermal {
 			polling-delay-passive = <100>;
@@ -2027,6 +2050,8 @@ gpu: gpu@...a0000 {
 		clocks = <&cru ACLK_GPU>;
 		#cooling-cells = <2>;
 		power-domains = <&power RK3399_PD_GPU>;
+		#powerzone-cells = <0>;
+		powerzone = <&PKG_PZ>;
 		status = "disabled";
 	};
 
-- 
2.25.1

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