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Date:   Sat, 27 Nov 2021 00:23:42 +0800
From:   Wei Fu <wefu@...hat.com>
To:     Christoph Hellwig <hch@....de>
Cc:     Guo Ren <guoren@...nel.org>, Anup Patel <Anup.Patel@....com>,
        Atish Patra <Atish.Patra@....com>,
        Christoph Müllner <christoph.muellner@...ll.eu>,
        Philipp Tomsich <philipp.tomsich@...ll.eu>,
        liush <liush@...winnertech.com>,
        Wei Wu (吴伟) <lazyparser@...il.com>,
        Drew Fustini <drew@...gleboard.org>,
        linux-riscv <linux-riscv@...ts.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        taiten.peng@...onical.com,
        Aniket Ponkshe <aniket.ponkshe@...onical.com>,
        Heinrich Schuchardt <heinrich.schuchardt@...onical.com>,
        Gordan Markus <gordan.markus@...onical.com>,
        Guo Ren <guoren@...ux.alibaba.com>,
        Arnd Bergmann <arnd@...db.de>, Chen-Yu Tsai <wens@...e.org>,
        Maxime Ripard <maxime@...no.tech>,
        Daniel Lustig <dlustig@...dia.com>,
        Greg Favor <gfavor@...tanamicro.com>,
        Andrea Mondelli <andrea.mondelli@...wei.com>,
        Jonathan Behrens <behrensj@....edu>,
        "Xinhaoqu (Freddie)" <xinhaoqu@...wei.com>,
        Bill Huffman <huffman@...ence.com>,
        Nick Kossifidis <mick@....forth.gr>,
        Allen Baum <allen.baum@...erantotech.com>,
        Josh Scheid <jscheid@...tanamicro.com>,
        Richard Trauben <rtrauben@...il.com>,
        Palmer Dabbelt <palmer@...belt.com>
Subject: Re: [RESEND PATCH V3 0/2] riscv: add RISC-V Svpbmt Standard Extension supports

Hi Christoph,

On Mon, Nov 8, 2021 at 3:52 PM Christoph Hellwig <hch@....de> wrote:
>
> On Sun, Nov 07, 2021 at 03:12:51PM +0800, Wei Fu wrote:
> > How about
> >
> > config RISCV_SVPBMT
> > bool
> > depends on 64BIT && MMU
> > default y
>
> Yes.  You can shorten this a bit more using def_bool if you want.
Sorry for the late reply, OK, fixing it now
>

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