lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Date:   Sat, 27 Nov 2021 12:04:37 +0900
From:   Daniel Palmer <daniel@...f.com>
To:     Dafna Hirschfeld <dafna.hirschfeld@...labora.com>
Cc:     "open list:MEDIA INPUT INFRASTRUCTURE (V4L/DVB)" 
        <linux-media@...r.kernel.org>,
        Robert Beckett <bob.beckett@...labora.com>,
        Mauro Carvalho Chehab <mchehab@...nel.org>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        "open list:STAGING SUBSYSTEM" <linux-staging@...ts.linux.dev>,
        open list <linux-kernel@...r.kernel.org>,
        Laurent Pinchart <laurent.pinchart@...asonboard.com>,
        hverkuil@...all.nl, kernel@...labora.com, dafna3@...il.com,
        kiril.bicevski@...labora.com,
        Nas Chung <nas.chung@...psnmedia.com>,
        lafley.kim@...psnmedia.com, scott.woo@...psnmedia.com,
        olivier.crete@...labora.com, dan.carpenter@...cle.com,
        Randy Dunlap <rdunlap@...radead.org>
Subject: Re: [PATCH v3 3/6] staging: media: wave5: Add the v4l2 layer

Hi Dafna,

On Wed, 10 Nov 2021 at 21:09, Dafna Hirschfeld
<dafna.hirschfeld@...labora.com> wrote:
> +static int wave5_vpu_probe(struct platform_device *pdev)
> +{
> +       int ret = 0;
> +       struct vpu_device *dev;
> +       struct resource *res = NULL;
> +       const struct wave5_match_data *match_data;

.. snip ...

> +       dev->dev = &pdev->dev;
> +       dev->product_code = wave5_vdi_read_register(dev, VPU_PRODUCT_CODE_REGISTER);

You access a register here..

> +       ret = devm_clk_bulk_get_all(&pdev->dev, &dev->clks);
> +
> +       /* continue without clock, assume externally managed */
> +       if (ret < 0) {
> +               dev_warn(&pdev->dev, "unable to get clocks: %d\n", ret);
> +               ret = 0;
> +       }
> +       dev->num_clks = ret;
> +
> +       ret = clk_bulk_prepare_enable(dev->num_clks, dev->clks);
> +       if (ret) {
> +               dev_err(&pdev->dev, "failed to enable clocks: %d\n", ret);
> +               goto err_clk_prep_en;
> +       }

but only get and enable the clocks further down.

For anything that needs a clock enabled to access the register and
doesn't have it enabled when probe is called the CPU might lock up.
I found this out while trying to get this code working on another chip
that has one of these IP blocks.

Cheers,

Daniel

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ