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Message-ID: <YaQTWG6g8nNP7GGX@robh.at.kernel.org>
Date: Sun, 28 Nov 2021 17:40:08 -0600
From: Rob Herring <robh@...nel.org>
To: Horatiu Vultur <horatiu.vultur@...rochip.com>
Cc: davem@...emloft.net, kuba@...nel.org, UNGLinuxDriver@...rochip.com,
p.zabel@...gutronix.de, linux@...linux.org.uk, andrew@...n.ch,
netdev@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH net-next v4 1/6] dt-bindings: net: lan966x: Add
lan966x-switch bindings
On Fri, Nov 26, 2021 at 10:05:35AM +0100, Horatiu Vultur wrote:
> Document the lan966x switch device driver bindings
>
> Signed-off-by: Horatiu Vultur <horatiu.vultur@...rochip.com>
> ---
> .../net/microchip,lan966x-switch.yaml | 149 ++++++++++++++++++
> 1 file changed, 149 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/net/microchip,lan966x-switch.yaml
>
> diff --git a/Documentation/devicetree/bindings/net/microchip,lan966x-switch.yaml b/Documentation/devicetree/bindings/net/microchip,lan966x-switch.yaml
> new file mode 100644
> index 000000000000..9367491dd2d5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/microchip,lan966x-switch.yaml
> @@ -0,0 +1,149 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/net/microchip,lan966x-switch.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Microchip Lan966x Ethernet switch controller
> +
> +maintainers:
> + - Horatiu Vultur <horatiu.vultur@...rochip.com>
> +
> +description: |
> + The lan966x switch is a multi-port Gigabit AVB/TSN Ethernet Switch with
> + two integrated 10/100/1000Base-T PHYs. In addition to the integrated PHYs,
> + it supports up to 2RGMII/RMII, up to 3BASE-X/SERDES/2.5GBASE-X and up to
> + 2 Quad-SGMII/Quad-USGMII interfaces.
> +
> +properties:
> + $nodename:
> + pattern: "^switch@[0-9a-f]+$"
> +
> + compatible:
> + const: microchip,lan966x-switch
> +
> + reg:
> + items:
> + - description: cpu target
> + - description: general control block target
> +
> + reg-names:
> + items:
> + - const: cpu
> + - const: gcb
> +
> + interrupts:
> + minItems: 1
> + items:
> + - description: register based extraction
> + - description: frame dma based extraction
> +
> + interrupt-names:
> + minItems: 1
> + items:
> + - const: xtr
> + - const: fdma
> +
> + resets:
> + items:
> + - description: Reset controller used for switch core reset (soft reset)
> + - description: Reset controller used for releasing the phy from reset
> +
> + reset-names:
> + items:
> + - const: switch
> + - const: phy
> +
> + ethernet-ports:
> + type: object
> + patternProperties:
> + "^port@[0-9a-f]+$":
> + type: object
This needs a reference to ethernet-controller.yaml so that all the
properties have a type applied.
See dsa.yaml for an example.
> +
> + properties:
> + '#address-cells':
> + const: 1
> + '#size-cells':
> + const: 0
> +
> + reg:
> + description:
> + Switch port number
> +
> + phys:
> + description:
> + Phandle of a Ethernet SerDes PHY
> +
> + phy-mode:
> + description:
> + This specifies the interface used by the Ethernet SerDes towards
> + the PHY or SFP.
Presumably only some subset of all defined modes are possible on this
h/w?
> +
> + phy-handle:
> + description:
> + Phandle of a Ethernet PHY.
> +
> + sfp:
> + description:
> + Phandle of an SFP.
> +
> + managed: true
> +
> + required:
> + - reg
> + - phys
> + - phy-mode
> +
> + oneOf:
> + - required:
> + - phy-handle
> + - required:
> + - sfp
> + - managed
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - interrupts
> + - interrupt-names
> + - resets
> + - reset-names
> + - ethernet-ports
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + switch: switch@...00000 {
> + compatible = "microchip,lan966x-switch";
> + reg = <0xe0000000 0x0100000>,
> + <0xe2000000 0x0800000>;
> + reg-names = "cpu", "gcb";
> + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "xtr";
> + resets = <&switch_reset 0>, <&phy_reset 0>;
> + reset-names = "switch", "phy";
> + ethernet-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port0: port@0 {
> + reg = <0>;
> + phy-handle = <&phy0>;
> + phys = <&serdes 0 0>;
> + phy-mode = "gmii";
> + };
> +
> + port1: port@1 {
> + reg = <1>;
> + sfp = <&sfp_eth1>;
> + managed = "in-band-status";
> + phys = <&serdes 2 4>;
> + phy-mode = "sgmii";
> + };
> + };
> + };
> +
> +...
> --
> 2.33.0
>
>
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