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Message-Id: <20211129014007.286478-1-wefu@redhat.com>
Date: Mon, 29 Nov 2021 09:40:05 +0800
From: wefu@...hat.com
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Subject: [PATCH V4 0/2] riscv: add RISC-V Svpbmt Standard Extension supports
From: Fu Wei <wefu@...hat.com>
This patch follows the RISC-V standard Svpbmt extension in
privilege spec to solve the non-coherent SOC DMA synchronization
issues.
The svpbmt PTE format:
| 63 | 62-61 | 60-8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
N MT RSW D A G U X W R V
^
Of the Reserved bits [63:54] in a leaf PTE, the bits [62:61] are used as
the MT (aka MemType) field. This field specifies one of three memory types
as shown in the following tableļ¼
MemType RISC-V Description
---------- ------------------------------------------------
00 - PMA Normal Cacheable, No change to implied PMA memory type
01 - NC Non-cacheable, idempotent, weakly-ordered Main Memory
10 - IO Non-cacheable, non-idempotent, strongly-ordered I/O memory
11 - Rsvd Reserved for future standard use
The standard protection_map[] needn't be modified because the "PMA"
type keeps the highest bits zero.
And the whole modification is limited in the arch/riscv/* and using
a global variable(__svpbmt) as _PAGE_MASK/IO/NOCACHE for pgprot_noncached
(&writecombine) in pgtable.h. We also add _PAGE_CHG_MASK to filter
PFN than before.
Enable it in devicetree - (Add "riscv,svpbmt" in the mmu of cpu node)
- mmu:
riscv,svpmbt
Wei Fu (2):
dt-bindings: riscv: add MMU Standard Extensions support for Svpbmt
riscv: add RISC-V Svpbmt extension supports
.../devicetree/bindings/riscv/cpus.yaml | 10 +++++
arch/riscv/include/asm/fixmap.h | 2 +-
arch/riscv/include/asm/pgtable-64.h | 21 ++++++++--
arch/riscv/include/asm/pgtable-bits.h | 39 ++++++++++++++++++-
arch/riscv/include/asm/pgtable.h | 39 ++++++++++++++-----
arch/riscv/kernel/cpufeature.c | 35 +++++++++++++++++
arch/riscv/mm/init.c | 5 +++
7 files changed, 136 insertions(+), 15 deletions(-)
--
2.25.4
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