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Message-Id: <20211130175740.2216591-1-aaelhaj@google.com>
Date: Tue, 30 Nov 2021 12:57:40 -0500
From: Ali El-Haj-Mahmoud <aaelhaj@...gle.com>
To: linux-arm-kernel@...ts.infradead.org,
linux-aspeed@...ts.ozlabs.org, linux-kernel@...r.kernel.org
Cc: Rob Herring <robh+dt@...nel.org>, Joel Stanley <joel@....id.au>,
Andrew Jeffery <andrew@...id.au>, Oskar Sneft <osk@...gle.com>,
Ali El-Haj-Mahmoud <aaelhaj@...gle.com>
Subject: [PATCH] S8036 DTS changes:
- Allow VUART and SuperIO to coexist.
- Minor formatting.
---
.../linux-aspeed/aspeed-bmc-tyan-s8036.dts | 23 +++++++++++++++----
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/meta-tyan/meta-s8036/recipes-kernel/linux/linux-aspeed/aspeed-bmc-tyan-s8036.dts b/meta-tyan/meta-s8036/recipes-kernel/linux/linux-aspeed/aspeed-bmc-tyan-s8036.dts
index 30b68ce89..7f650f6c8 100644
--- a/meta-tyan/meta-s8036/recipes-kernel/linux/linux-aspeed/aspeed-bmc-tyan-s8036.dts
+++ b/meta-tyan/meta-s8036/recipes-kernel/linux/linux-aspeed/aspeed-bmc-tyan-s8036.dts
@@ -127,10 +127,23 @@
status = "okay";
};
+&uart_routing {
+ status = "okay";
+};
+
&vuart {
status = "okay";
- aspeed,lpc-io-reg = <0x3f8>;
- aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
+
+ /* We enable the VUART here, but leave it in a state that does
+ * not interfere with the SuperIO. The goal is to have both the
+ * VUART and the SuperIO available and decide at runtime whether
+ * the VUART should actually be used. For that reason, configure
+ * an "invalid" IO address and an IRQ that is not used by the
+ * BMC.
+ */
+
+ aspeed,lpc-io-reg = <0xffff>;
+ aspeed,lpc-interrupts = <15 IRQ_TYPE_LEVEL_HIGH>;
};
&lpc_ctrl {
@@ -340,7 +353,7 @@
&kcs1 {
status = "okay";
- aspeed,lpc-io-reg = <0xca8>;
+ aspeed,lpc-io-reg = <0xca8>;
};
&kcs3 {
@@ -385,7 +398,7 @@
/*A6*/ "",
/*A7*/ "",
/*B0-B7*/ "","","","","","","","",
- /*C0-C7*/ "","","","","","","","",
+ /*C0-C7*/ "","","","","","","","",
/*D0*/ "",
/*D1*/ "",
/*D2*/ "power-chassis-good", /* in: PWR_GOOD_LED -- Check if this is Z3?*/
@@ -447,6 +460,6 @@
/*AA5*/ "",
/*AA6*/ "",
/*AA7*/ "BMC_ASSERT_BMC_READY",
- /*AB0*/ "BMC_SPD_SEL",
+ /*AB0*/ "BMC_SPD_SEL",
/*AB1-AB7*/ "","","","","","","";
};
--
2.34.0.rc2.393.gf8c9666880-goog
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