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Message-ID: <1638262465-10790-5-git-send-email-harsha.harsha@xilinx.com>
Date:   Tue, 30 Nov 2021 14:24:23 +0530
From:   Harsha <harsha.harsha@...inx.com>
To:     <herbert@...dor.apana.org.au>, <davem@...emloft.net>,
        <linux-crypto@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <michal.simek@...inx.com>, <linux-arm-kernel@...ts.infradead.org>,
        <robh+dt@...nel.org>, <devicetree@...r.kernel.org>
CC:     <saratcha@...inx.com>, <harshj@...inx.com>,
        Harsha <harsha.harsha@...inx.com>
Subject: [RFC PATCH 4/6] arm64: dts: zynqmp: Add Xilinx SHA3 node

This patch adds a SHA3 DT node for Xilinx ZynqMP SoC.

Signed-off-by: Harsha <harsha.harsha@...inx.com>
---
 arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 74e6644..33b7ef6 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -174,6 +174,10 @@
 				compatible = "xlnx,zynqmp-aes";
 			};
 
+			xlnx_sha3_384: sha384 {
+				compatible = "xlnx,zynqmp-sha3-384";
+			};
+
 			zynqmp_reset: reset-controller {
 				compatible = "xlnx,zynqmp-reset";
 				#reset-cells = <1>;
-- 
1.8.2.1

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