linux-kernel - Re: [PATCH V4 1/2] dt-bindings: riscv: add MMU Standard Extensions support for Svpbmt

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Message-ID: <CA+YCwKnwkdWY2b6XtAwM=ZmQ=mVMMDnG3s746GQA_DLhLVtBSg@mail.gmail.com>
Date:   Wed, 1 Dec 2021 10:58:46 +0800
From:   Wei Fu <wefu@...hat.com>
To:     Heiko Stübner <heiko@...ech.de>
Cc:     Anup Patel <anup.patel@....com>, atishp04@...il.com,
        Palmer Dabbelt <palmer@...belt.com>,
        Guo Ren <guoren@...nel.org>,
        Christoph Müllner <christoph.muellner@...ll.eu>,
        Philipp Tomsich <philipp.tomsich@...ll.eu>,
        Christoph Hellwig <hch@....de>,
        Liu Shaohua <liush@...winnertech.com>,
        Wei Wu (吴伟) <lazyparser@...il.com>,
        Drew Fustini <drew@...gleboard.org>,
        linux-riscv <linux-riscv@...ts.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        taiten.peng@...onical.com,
        Aniket Ponkshe <aniket.ponkshe@...onical.com>,
        Heinrich Schuchardt <heinrich.schuchardt@...onical.com>,
        Gordan Markus <gordan.markus@...onical.com>,
        Guo Ren <guoren@...ux.alibaba.com>,
        Arnd Bergmann <arnd@...db.de>, Chen-Yu Tsai <wens@...e.org>,
        Maxime Ripard <maxime@...no.tech>,
        Daniel Lustig <dlustig@...dia.com>,
        Greg Favor <gfavor@...tanamicro.com>,
        Andrea Mondelli <andrea.mondelli@...wei.com>,
        Jonathan Behrens <behrensj@....edu>,
        Xinhaoqu <xinhaoqu@...wei.com>,
        Bill Huffman <huffman@...ence.com>,
        Nick Kossifidis <mick@....forth.gr>,
        Allen Baum <allen.baum@...erantotech.com>,
        Josh Scheid <jscheid@...tanamicro.com>,
        Richard Trauben <rtrauben@...il.com>,
        Anup Patel <anup@...infault.org>,
        Rob Herring <robh+dt@...nel.org>
Subject: Re: [PATCH V4 1/2] dt-bindings: riscv: add MMU Standard Extensions
 support for Svpbmt

Hi Heiko,
Thanks for your correction ,  this was my typo when I did the "sed" to
replace the word.
I need to make a V5 ASAP

On Wed, Dec 1, 2021 at 2:46 AM Heiko Stübner <heiko@...ech.de> wrote:
>
> Am Montag, 29. November 2021, 02:40:06 CET schrieb wefu@...hat.com:
> > From: Wei Fu <wefu@...hat.com>
> >
> > Previous patch has added svpbmt in arch/riscv and add "riscv,svpmbt"
> > in the DT mmu node. Update dt-bindings related property here.
> >
> > Signed-off-by: Wei Fu <wefu@...hat.com>
> > Co-developed-by: Guo Ren <guoren@...nel.org>
> > Signed-off-by: Guo Ren <guoren@...nel.org>
> > Cc: Anup Patel <anup@...infault.org>
> > Cc: Palmer Dabbelt <palmer@...belt.com>
> > Cc: Rob Herring <robh+dt@...nel.org>
> > ---
> >  Documentation/devicetree/bindings/riscv/cpus.yaml | 10 ++++++++++
> >  1 file changed, 10 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > index aa5fb64d57eb..9ff9cbdd8a85 100644
> > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > @@ -63,6 +63,16 @@ properties:
> >        - riscv,sv48
> >        - riscv,none
> >
> > +  mmu:
> > +    description:
> > +      Describes the CPU's MMU Standard Extensions support.
> > +      These values originate from the RISC-V Privileged
> > +      Specification document, available from
> > +      https://riscv.org/specifications/
> > +    $ref: '/schemas/types.yaml#/definitions/string'
> > +    enum:
> > +      - riscv,svpmbt
>
> shouldn't that be "riscv,svpbmt" ? [the m is at the wrong location it seems]
>
> > +
> >    riscv,isa:
> >      description:
> >        Identifies the specific RISC-V instruction set architecture
> >
>
>
>
>