| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <20211202075105.195664-2-avolmat@me.com>
Date: Thu, 2 Dec 2021 08:50:54 +0100
From: Alain Volmat <avolmat@...com>
To: patrice.chotard@...com, robh+dt@...nel.org, mark.rutland@....com,
linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Cc: avolmat@...com
Subject: [PATCH 01/12] ARM: dts: sti: ensure unique unit-address in stih407-clock
Move quadfs and a9-mux clocks nodes into clockgen nodes so
that they can get the reg property from the parent node and
ensure only one node has the address.
Signed-off-by: Alain Volmat <avolmat@...com>
---
arch/arm/boot/dts/stih407-clock.dtsi | 101 ++++++++++++---------------
1 file changed, 46 insertions(+), 55 deletions(-)
diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi
index 9cce9541e26b..350bcfcf498b 100644
--- a/arch/arm/boot/dts/stih407-clock.dtsi
+++ b/arch/arm/boot/dts/stih407-clock.dtsi
@@ -29,7 +29,7 @@ clocks {
*/
clockgen-a9@...0000 {
compatible = "st,clkgen-c32";
- reg = <0x92b0000 0xffff>;
+ reg = <0x92b0000 0x10000>;
clockgen_a9_pll: clockgen-a9-pll {
#clock-cells = <1>;
@@ -37,32 +37,27 @@ clockgen_a9_pll: clockgen-a9-pll {
clocks = <&clk_sysin>;
};
- };
- /*
- * ARM CPU related clocks.
- */
- clk_m_a9: clk-m-a9@...0000 {
- #clock-cells = <0>;
- compatible = "st,stih407-clkgen-a9-mux";
- reg = <0x92b0000 0x10000>;
-
- clocks = <&clockgen_a9_pll 0>,
- <&clockgen_a9_pll 0>,
- <&clk_s_c0_flexgen 13>,
- <&clk_m_a9_ext2f_div2>;
+ clk_m_a9: clk-m-a9 {
+ #clock-cells = <0>;
+ compatible = "st,stih407-clkgen-a9-mux";
+ clocks = <&clockgen_a9_pll 0>,
+ <&clockgen_a9_pll 0>,
+ <&clk_s_c0_flexgen 13>,
+ <&clk_m_a9_ext2f_div2>;
- /*
- * ARM Peripheral clock for timers
- */
- arm_periph_clk: clk-m-a9-periphs {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
+ /*
+ * ARM Peripheral clock for timers
+ */
+ arm_periph_clk: clk-m-a9-periphs {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
- clocks = <&clk_m_a9>;
- clock-div = <2>;
- clock-mult = <1>;
+ clocks = <&clk_m_a9>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
};
};
@@ -87,14 +82,6 @@ clk_s_a0_flexgen: clk-s-a0-flexgen {
};
};
- clk_s_c0_quadfs: clk-s-c0-quadfs@...3000 {
- #clock-cells = <1>;
- compatible = "st,quadfs-pll";
- reg = <0x9103000 0x1000>;
-
- clocks = <&clk_sysin>;
- };
-
clk_s_c0: clockgen-c@...3000 {
compatible = "st,clkgen-c32";
reg = <0x9103000 0x1000>;
@@ -113,6 +100,13 @@ clk_s_c0_pll1: clk-s-c0-pll1 {
clocks = <&clk_sysin>;
};
+ clk_s_c0_quadfs: clk-s-c0-quadfs {
+ #clock-cells = <1>;
+ compatible = "st,quadfs-pll";
+
+ clocks = <&clk_sysin>;
+ };
+
clk_s_c0_flexgen: clk-s-c0-flexgen {
#clock-cells = <1>;
compatible = "st,flexgen", "st,flexgen-stih407-c0";
@@ -142,18 +136,17 @@ clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
};
};
- clk_s_d0_quadfs: clk-s-d0-quadfs@...4000 {
- #clock-cells = <1>;
- compatible = "st,quadfs-d0";
- reg = <0x9104000 0x1000>;
-
- clocks = <&clk_sysin>;
- };
-
clockgen-d0@...4000 {
compatible = "st,clkgen-c32";
reg = <0x9104000 0x1000>;
+ clk_s_d0_quadfs: clk-s-d0-quadfs {
+ #clock-cells = <1>;
+ compatible = "st,quadfs-d0";
+
+ clocks = <&clk_sysin>;
+ };
+
clk_s_d0_flexgen: clk-s-d0-flexgen {
#clock-cells = <1>;
compatible = "st,flexgen", "st,flexgen-stih407-d0";
@@ -166,18 +159,17 @@ clk_s_d0_flexgen: clk-s-d0-flexgen {
};
};
- clk_s_d2_quadfs: clk-s-d2-quadfs@...6000 {
- #clock-cells = <1>;
- compatible = "st,quadfs-d2";
- reg = <0x9106000 0x1000>;
-
- clocks = <&clk_sysin>;
- };
-
clockgen-d2@...6000 {
compatible = "st,clkgen-c32";
reg = <0x9106000 0x1000>;
+ clk_s_d2_quadfs: clk-s-d2-quadfs {
+ #clock-cells = <1>;
+ compatible = "st,quadfs-d2";
+
+ clocks = <&clk_sysin>;
+ };
+
clk_s_d2_flexgen: clk-s-d2-flexgen {
#clock-cells = <1>;
compatible = "st,flexgen", "st,flexgen-stih407-d2";
@@ -192,18 +184,17 @@ clk_s_d2_flexgen: clk-s-d2-flexgen {
};
};
- clk_s_d3_quadfs: clk-s-d3-quadfs@...7000 {
- #clock-cells = <1>;
- compatible = "st,quadfs-d3";
- reg = <0x9107000 0x1000>;
-
- clocks = <&clk_sysin>;
- };
-
clockgen-d3@...7000 {
compatible = "st,clkgen-c32";
reg = <0x9107000 0x1000>;
+ clk_s_d3_quadfs: clk-s-d3-quadfs {
+ #clock-cells = <1>;
+ compatible = "st,quadfs-d3";
+
+ clocks = <&clk_sysin>;
+ };
+
clk_s_d3_flexgen: clk-s-d3-flexgen {
#clock-cells = <1>;
compatible = "st,flexgen", "st,flexgen-stih407-d3";
--
2.25.1
Powered by blists - more mailing lists