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Message-ID: <7f627adcaf0c8a8d0ffc8696658d3e400a750e62.camel@ew.tq-group.com>
Date: Thu, 02 Dec 2021 10:20:54 +0100
From: Matthias Schiffer <matthias.schiffer@...tq-group.com>
To: Tudor Ambarus <tudor.ambarus@...rochip.com>,
Michael Walle <michael@...le.cc>,
Pratyush Yadav <p.yadav@...com>,
Miquel Raynal <miquel.raynal@...tlin.com>,
Richard Weinberger <richard@....at>,
Vignesh Raghavendra <vigneshr@...com>
Cc: linux-mtd@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 1/2] mtd: spi-nor: micron-st: make
mt25ql02g/mt25qu02g match more specific, add 4B opcodes
On Thu, 2021-10-07 at 14:08 +0200, Matthias Schiffer wrote:
> Change the mt25ql02g/mt25qu02g entries to include SPI_NOR_4B_OPCODES.
> In
> addition, the SPI_NOR_DUAL_READ flag is added to mt25ql02g; this
> seems
> to have been an accidental omission, as mt25ql02g and mt25qu02g
> should
> support the same features.
>
> In addition, the entries are made more specific by matching on the
> mt25q
> extended ID, like it is already done for the smaller n25q
> derivatives.
> It is unclear whether n25q derivatives with 2Gbit exist that do not
> support 4B opcodes (like it is the case for sizes up to 512MBit), so
> we
> do not have a match for such variants anymore (as we wouldn't even
> know
> how to name such hypothetical models).
>
> The changes were tested with a mt25qu01g, which should support the
> same
> features as the mt25ql02g/mt25qu02g.
>
> Signed-off-by: Matthias Schiffer <matthias.schiffer@...tq-group.com>
> ---
ping
>
> v2:
> - add extended ID match
> - add back NO_CHIP_ERASE
>
> drivers/mtd/spi-nor/micron-st.c | 14 ++++++++------
> 1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-
> nor/micron-st.c
> index c224e59820a1..a000a0790ecd 100644
> --- a/drivers/mtd/spi-nor/micron-st.c
> +++ b/drivers/mtd/spi-nor/micron-st.c
> @@ -180,12 +180,14 @@ static const struct flash_info st_parts[] = {
> { "n25q00a", INFO(0x20bb21, 0, 64 * 1024, 2048,
> SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
> NO_CHIP_ERASE) },
> - { "mt25ql02g", INFO(0x20ba22, 0, 64 * 1024, 4096,
> - SECT_4K | USE_FSR | SPI_NOR_QUAD_READ |
> - NO_CHIP_ERASE) },
> - { "mt25qu02g", INFO(0x20bb22, 0, 64 * 1024, 4096,
> - SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
> - SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> + { "mt25ql02g", INFO6(0x20ba22, 0x104400, 64 * 1024, 4096,
> + SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
> + SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
> + NO_CHIP_ERASE) },
> + { "mt25qu02g", INFO6(0x20bb22, 0x104400, 64 * 1024, 4096,
> + SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
> + SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
> + NO_CHIP_ERASE) },
>
> { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
> { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
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