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Message-Id: <20211202095255.165797-7-herve.codina@bootlin.com>
Date: Thu, 2 Dec 2021 10:52:55 +0100
From: Herve Codina <herve.codina@...tlin.com>
To: Viresh Kumar <vireshk@...nel.org>,
Shiraz Hashim <shiraz.linux.kernel@...il.com>, soc@...nel.org,
Rob Herring <robh+dt@...nel.org>,
Thomas Gleixner <tglx@...utronix.de>,
Marc Zyngier <maz@...nel.org>,
Linus Walleij <linus.walleij@...aro.org>
Cc: linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-gpio@...r.kernel.org,
Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
Herve Codina <herve.codina@...tlin.com>
Subject: [PATCH 6/6] ARM: dts: spear3xx: Add spear320s dtsi
The SPEAr320s SOC is a SPEAr320 SOC variant.
Mostly identical to the SPEAr320 SOC variant, it has a
new interrupt routing for PL_PGIOs.
Add spear320s.dtsi to handle SPEAr320s SOC
Signed-off-by: Herve Codina <herve.codina@...tlin.com>
---
arch/arm/boot/dts/spear320s.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
create mode 100644 arch/arm/boot/dts/spear320s.dtsi
diff --git a/arch/arm/boot/dts/spear320s.dtsi b/arch/arm/boot/dts/spear320s.dtsi
new file mode 100644
index 000000000000..133236dc190d
--- /dev/null
+++ b/arch/arm/boot/dts/spear320s.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * DTS file for SPEAr320s SoC
+ *
+ * Copyright 2021 Herve Codina <herve.codina@...tlin.com>
+ */
+
+/include/ "spear320.dtsi"
+
+/ {
+ ahb {
+ apb {
+ gpiopinctrl: gpio@...00000 {
+ /*
+ * The "RM0321 SPEAr320s address and map
+ * registers" document mentions interrupt 6
+ * (NPGIO_INTR) for the PL_GPIO interrupt.
+ */
+ interrupts = <6>;
+ interrupt-parent = <&shirq>;
+ };
+ };
+ };
+};
--
2.31.1
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